DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | TRUTH TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | AC OPERATING REQUIREMENTS | VERILOG MODEL
The 'F379 is a 4-bit register with buffered common Enable. This device is similar to the 'F175 but features the common Enable rather than common Master Reset. o EDGE-TRIGGERED D-TYPE INPUTS o BUFFERED POSITIVE EDGE-TRIGGERED CLOCK o BUFFERED COMMON ENABLE INPUT o TRUE AND COMPLEMENT OUTPUTS
The 'F379 consists of four edge-triggered D-type flip-flops with individual D inputs and Q and /Q outputs. The Clock (CP) and Enable (/E) inputs are common to all flip-flops. When the /E input is HIGH, the register will retain the present data independent of the CP input. The Dn and /E inputs can change when the clock is in either state, provided that the recommended setup and hold times are observed.
Pin Function Pin Function --- ------------------------- --- ------------------------- 1 /E Enable input 16 Vcc 2 Q0 True output 0 15 Q3 True output 3 3 /Q0 Complement output 0 14 /Q3 Complement output 3 4 D0 Data input 0 13 D3 Data input 3 5 D1 Data input 1 12 D2 Data input 2 6 /Q1 Complement output 1 11 /Q2 Complement output 2 7 Q1 True output 1 10 Q2 True output 2 8 GND 9 CP Clock Pulse
/E CP Dn Qn /Qn -- -- -- --------- --------- H ^ X No Change No Change L ^ H H L L ^ L L H H = HIGH voltage level; L = LOW voltage level; X = immaterial; ^ = LOW-to-HIGH clock transition (rising edge). No Change = the outputs hold the state they had before the clock pulse.
Pin Names Description U.L. HIGH/LOW ---------- --------------------------------------- ------------- /E Enable Input (Active LOW) 0.5 / 0.375 D0 - D3 Data Inputs 0.5 / 0.375 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 Q0 - Q3 Flip-flop Outputs 25 / 12.5 /Q0 - /Q3 Complement Outputs 25 / 12.5
Conditions: Vcc = Max; D, /E = Gnd; CP = ^ (rising edge). Symbol Parameter Min Typ Max Units ------ -------------------- --- --- --- ----- ICC Power Supply Current 27 mA
Symbol Parameter Min Typ Max Units ------ ----------------------- --- --- --- ----- fmax Maximum Clock Frequency 110 150 -- MHz tPLH Prop Delay CP to Qn -- 6.1 -- ns tPHL Prop Delay CP to Qn -- 6.3 -- ns
Symbol Parameter Min Typ Max Units ------ ---------------------------- --- --- --- ----- ts (H) Setup Time, HIGH -- Dn to CP 3.0 -- -- ns ts (L) Setup Time, LOW -- Dn to CP 3.0 -- -- ns th (H) Hold Time, HIGH -- Dn to CP 2.0 -- -- ns th (L) Hold Time, LOW -- Dn to CP 2.0 -- -- ns ts (H) Setup Time, HIGH -- /E to CP 5.0 -- -- ns ts (L) Setup Time, LOW -- /E to CP 6.0 -- -- ns th (H) Hold Time, HIGH -- /E to CP 0 -- -- ns th (L) Hold Time, LOW -- /E to CP 0 -- -- ns tw (L) CP Pulse Width LOW 4.5 -- -- ns
Data sheet transcription as plain text
// ============================================================================ // f379.v — 54F/74F379 Quad Parallel Register (With Enable) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F379.txt (1980 Fairchild FAST Data Book, // pages 4-105 ... 4-107; preliminary data sheet) // // Four edge-triggered D-type flip-flops with individual D inputs and both // true (Q) and complement (Q_n) outputs. Clock (CP) and Enable (E_n) are // common to all four. On the LOW-to-HIGH CP transition with E_n LOW, D is // stored; with E_n HIGH the register retains the present data independent // of the CP input. There are no asynchronous inputs. // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). // The preliminary data sheet gives TYPICAL values only (Min/Max columns // left blank), so each specparam carries just the typ value. // The data sheet characterizes CP to Q_n only; the CP to Q_n-bar paths // reuse the same values (no separate figures are given for the complement // outputs). // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f379 ( input wire e_n, // enable (active LOW), common input wire cp, // clock pulse (active rising edge), common input wire d0, // data input 0 output reg q0, // true output 0 output reg q0_n, // complement output 0 input wire d1, // data input 1 output reg q1, // true output 1 output reg q1_n, // complement output 1 input wire d2, // data input 2 output reg q2, // true output 2 output reg q2_n, // complement output 2 input wire d3, // data input 3 output reg q3, // true output 3 output reg q3_n // complement output 3 ); // Enable is synchronous: it only qualifies the rising clock edge, so // changing E_n or D while CP is static has no effect on the outputs. always @(posedge cp) begin if (!e_n) begin q0 <= d0; q0_n <= ~d0; end end always @(posedge cp) begin if (!e_n) begin q1 <= d1; q1_n <= ~d1; end end always @(posedge cp) begin if (!e_n) begin q2 <= d2; q2_n <= ~d2; end end always @(posedge cp) begin if (!e_n) begin q3 <= d3; q3_n <= ~d3; end end specify // Propagation delay CP to Q_n (data sheet typ only: tPLH 6.1, // tPHL 6.3 ns; min/max blank on preliminary sheet). The sheet // gives no separate CP to Q_n-bar figures; the complement paths // reuse these values (see header note). specparam tlh_cp_q = 6.1; specparam thl_cp_q = 6.3; (cp => q0) = (tlh_cp_q, thl_cp_q); (cp => q0_n) = (tlh_cp_q, thl_cp_q); (cp => q1) = (tlh_cp_q, thl_cp_q); (cp => q1_n) = (tlh_cp_q, thl_cp_q); (cp => q2) = (tlh_cp_q, thl_cp_q); (cp => q2_n) = (tlh_cp_q, thl_cp_q); (cp => q3) = (tlh_cp_q, thl_cp_q); (cp => q3_n) = (tlh_cp_q, thl_cp_q); // AC operating requirements (data sheet, +25 C 5.0 V minima): // D to CP: ts(H) 3.0, ts(L) 3.0, th(H) 2.0, th(L) 2.0 ns. // E_n to CP: ts(H) 5.0, ts(L) 6.0, th(H) 0, th(L) 0 ns. // tw(L) CP 4.5 ns. (The sheet lists no CP HIGH pulse width; // fmax 110 min / 150 typ MHz per the AC Characteristics table.) // Icarus Verilog does not support timing checks; kept (guarded) // for simulators that do. `ifndef __ICARUS__ specparam ts_h = 3.0; specparam ts_l = 3.0; specparam th_h = 2.0; specparam th_l = 2.0; specparam ts_e_h = 5.0; specparam ts_e_l = 6.0; specparam th_e_h = 0; specparam th_e_l = 0; specparam tw_cp_l = 4.5; // Dn's ts(H) and ts(L) are both 3.0 and its th(H)/th(L) both 2.0, so // one unqualified check each covers the sheet's pair. /E is the // exception: ts(H) 5.0 against ts(L) 6.0, so its two arrival edges // are checked separately. th(H)/th(L) for /E are both 0. $setup(d0, posedge cp, ts_h); $setup(d1, posedge cp, ts_h); $setup(d2, posedge cp, ts_h); $setup(d3, posedge cp, ts_h); $setup(posedge e_n, posedge cp, ts_e_h); $setup(negedge e_n, posedge cp, ts_e_l); $hold(posedge cp, d0, th_h); $hold(posedge cp, d1, th_h); $hold(posedge cp, d2, th_h); $hold(posedge cp, d3, th_h); $hold(posedge cp, e_n, th_e_h); $width(negedge cp, tw_cp_l); `endif endspecify endmodule