======================================================================== 74F379 QUAD PARALLEL REGISTER (WITH ENABLE) ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-105 ... 4-107 Status: PRELIMINARY -- page 4-105 carries a "Preliminary" watermark. Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F379 is a 4-bit register with buffered common Enable. This device is similar to the 'F175 but features the common Enable rather than common Master Reset. o EDGE-TRIGGERED D-TYPE INPUTS o BUFFERED POSITIVE EDGE-TRIGGERED CLOCK o BUFFERED COMMON ENABLE INPUT o TRUE AND COMPLEMENT OUTPUTS FUNCTIONAL DESCRIPTION ---------------------- The 'F379 consists of four edge-triggered D-type flip-flops with individual D inputs and Q and /Q outputs. The Clock (CP) and Enable (/E) inputs are common to all flip-flops. When the /E input is HIGH, the register will retain the present data independent of the CP input. The Dn and /E inputs can change when the clock is in either state, provided that the recommended setup and hold times are observed. CONNECTION DIAGRAM (16-pin DIP) ------------------------------- Pin Function Pin Function --- ------------------------- --- ------------------------- 1 /E Enable input 16 Vcc 2 Q0 True output 0 15 Q3 True output 3 3 /Q0 Complement output 0 14 /Q3 Complement output 3 4 D0 Data input 0 13 D3 Data input 3 5 D1 Data input 1 12 D2 Data input 2 6 /Q1 Complement output 1 11 /Q2 Complement output 2 7 Q1 True output 1 10 Q2 True output 2 8 GND 9 CP Clock Pulse TRUTH TABLE ----------- /E CP Dn Qn /Qn -- -- -- --------- --------- H ^ X No Change No Change L ^ H H L L ^ L L H H = HIGH voltage level; L = LOW voltage level; X = immaterial; ^ = LOW-to-HIGH clock transition (rising edge). No Change = the outputs hold the state they had before the clock pulse. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW ---------- --------------------------------------- ------------- /E Enable Input (Active LOW) 0.5 / 0.375 D0 - D3 Data Inputs 0.5 / 0.375 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 Q0 - Q3 Flip-flop Outputs 25 / 12.5 /Q0 - /Q3 Complement Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Conditions: Vcc = Max; D, /E = Gnd; CP = ^ (rising edge). Symbol Parameter Min Typ Max Units ------ -------------------- --- --- --- ----- ICC Power Supply Current 27 mA AC CHARACTERISTICS ------------------ Symbol Parameter Min Typ Max Units ------ ----------------------- --- --- --- ----- fmax Maximum Clock Frequency 110 150 -- MHz tPLH Prop Delay CP to Qn -- 6.1 -- ns tPHL Prop Delay CP to Qn -- 6.3 -- ns AC OPERATING REQUIREMENTS ------------------------- Symbol Parameter Min Typ Max Units ------ ---------------------------- --- --- --- ----- ts (H) Setup Time, HIGH -- Dn to CP 3.0 -- -- ns ts (L) Setup Time, LOW -- Dn to CP 3.0 -- -- ns th (H) Hold Time, HIGH -- Dn to CP 2.0 -- -- ns th (L) Hold Time, LOW -- Dn to CP 2.0 -- -- ns ts (H) Setup Time, HIGH -- /E to CP 5.0 -- -- ns ts (L) Setup Time, LOW -- /E to CP 6.0 -- -- ns th (H) Hold Time, HIGH -- /E to CP 0 -- -- ns th (L) Hold Time, LOW -- /E to CP 0 -- -- ns tw (L) CP Pulse Width LOW 4.5 -- -- ns