// ============================================================================
// f379.v — 54F/74F379 Quad Parallel Register (With Enable)
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F379.txt (1980 Fairchild FAST Data Book,
//         pages 4-105 ... 4-107; preliminary data sheet)
//
// Four edge-triggered D-type flip-flops with individual D inputs and both
// true (Q) and complement (Q_n) outputs. Clock (CP) and Enable (E_n) are
// common to all four. On the LOW-to-HIGH CP transition with E_n LOW, D is
// stored; with E_n HIGH the register retains the present data independent
// of the CP input. There are no asynchronous inputs.
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF).
// The preliminary data sheet gives TYPICAL values only (Min/Max columns
// left blank), so each specparam carries just the typ value.
// The data sheet characterizes CP to Q_n only; the CP to Q_n-bar paths
// reuse the same values (no separate figures are given for the complement
// outputs).
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f379 (
    input  wire e_n,        // enable (active LOW), common
    input  wire cp,         // clock pulse (active rising edge), common
    input  wire d0,         // data input 0
    output reg  q0,         // true output 0
    output reg  q0_n,       // complement output 0
    input  wire d1,         // data input 1
    output reg  q1,         // true output 1
    output reg  q1_n,       // complement output 1
    input  wire d2,         // data input 2
    output reg  q2,         // true output 2
    output reg  q2_n,       // complement output 2
    input  wire d3,         // data input 3
    output reg  q3,         // true output 3
    output reg  q3_n        // complement output 3
);

    // Enable is synchronous: it only qualifies the rising clock edge, so
    // changing E_n or D while CP is static has no effect on the outputs.
    always @(posedge cp) begin
        if (!e_n) begin
            q0   <= d0;
            q0_n <= ~d0;
        end
    end

    always @(posedge cp) begin
        if (!e_n) begin
            q1   <= d1;
            q1_n <= ~d1;
        end
    end

    always @(posedge cp) begin
        if (!e_n) begin
            q2   <= d2;
            q2_n <= ~d2;
        end
    end

    always @(posedge cp) begin
        if (!e_n) begin
            q3   <= d3;
            q3_n <= ~d3;
        end
    end

    specify
        // Propagation delay CP to Q_n (data sheet typ only: tPLH 6.1,
        // tPHL 6.3 ns; min/max blank on preliminary sheet). The sheet
        // gives no separate CP to Q_n-bar figures; the complement paths
        // reuse these values (see header note).
        specparam tlh_cp_q = 6.1;
        specparam thl_cp_q = 6.3;

        (cp => q0)   = (tlh_cp_q, thl_cp_q);
        (cp => q0_n) = (tlh_cp_q, thl_cp_q);
        (cp => q1)   = (tlh_cp_q, thl_cp_q);
        (cp => q1_n) = (tlh_cp_q, thl_cp_q);
        (cp => q2)   = (tlh_cp_q, thl_cp_q);
        (cp => q2_n) = (tlh_cp_q, thl_cp_q);
        (cp => q3)   = (tlh_cp_q, thl_cp_q);
        (cp => q3_n) = (tlh_cp_q, thl_cp_q);

        // AC operating requirements (data sheet, +25 C 5.0 V minima):
        // D to CP: ts(H) 3.0, ts(L) 3.0, th(H) 2.0, th(L) 2.0 ns.
        // E_n to CP: ts(H) 5.0, ts(L) 6.0, th(H) 0, th(L) 0 ns.
        // tw(L) CP 4.5 ns. (The sheet lists no CP HIGH pulse width;
        // fmax 110 min / 150 typ MHz per the AC Characteristics table.)
        // Icarus Verilog does not support timing checks; kept (guarded)
        // for simulators that do.
`ifndef __ICARUS__
        specparam ts_h = 3.0;
        specparam ts_l = 3.0;
        specparam th_h = 2.0;
        specparam th_l = 2.0;
        specparam ts_e_h = 5.0;
        specparam ts_e_l = 6.0;
        specparam th_e_h = 0;
        specparam th_e_l = 0;
        specparam tw_cp_l = 4.5;

        // Dn's ts(H) and ts(L) are both 3.0 and its th(H)/th(L) both 2.0, so
        // one unqualified check each covers the sheet's pair. /E is the
        // exception: ts(H) 5.0 against ts(L) 6.0, so its two arrival edges
        // are checked separately. th(H)/th(L) for /E are both 0.
        $setup(d0, posedge cp, ts_h);
        $setup(d1, posedge cp, ts_h);
        $setup(d2, posedge cp, ts_h);
        $setup(d3, posedge cp, ts_h);
        $setup(posedge e_n, posedge cp, ts_e_h);
        $setup(negedge e_n, posedge cp, ts_e_l);
        $hold(posedge cp, d0, th_h);
        $hold(posedge cp, d1, th_h);
        $hold(posedge cp, d2, th_h);
        $hold(posedge cp, d3, th_h);
        $hold(posedge cp, e_n, th_e_h);
        $width(negedge cp, tw_cp_l);
`endif
    endspecify

endmodule