DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | TRUTH TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F251 is a high speed 8-input digital multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. It can be used as universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided. o Multifunctional capability o On-chip select logic decoding o Inverting and non-inverting 3-state outputs
This device is a logical implementation of a single-pole, 8-position
switch with the switch position controlled by the state of three Select
inputs, S0, S1, S2. Both assertion and negation outputs are provided.
The Output Enable input (/OE) is active LOW. When it is activated, the
logic function provided at the output is:
Z = /OE * ( I0*/S0*/S1*/S2 + I1*S0*/S1*/S2 + I2*/S0*S1*/S2
+ I3*S0*S1*/S2 + I4*/S0*/S1*S2 + I5*S0*/S1*S2
+ I6*/S0*S1*S2 + I7*S0*S1*S2 )
When the Output Enable is HIGH, both outputs are in the high impedance
(high Z) state. This feature allows multiplexer expansion by tying the
outputs of up to 128 devices together. When the outputs of the 3-state
devices are tied together, all but one device must be in the high
impedance state to avoid high currents that would exceed the maximum
ratings. The Output Enable signals should be designed to ensure there
is no overlap in the active LOW portion of the enable voltages.
Pin Function Pin Function --- --------------------------------------------- --- ------------------------ 1 I3 Multiplexer input 3 16 Vcc 2 I2 Multiplexer input 2 15 I4 Multiplexer input 4 3 I1 Multiplexer input 1 14 I5 Multiplexer input 5 4 I0 Multiplexer input 0 13 I6 Multiplexer input 6 5 Z Multiplexer output 12 I7 Multiplexer input 7 6 /Z Complementary output 11 S0 Select input 0 7 /OE 3-State Output Enable Input (Active LOW) 10 S1 Select input 1 8 GND 9 S2 Select input 2
/OE S2 S1 S0 /Z Z --- -- -- -- --- --- H X X X Z Z L L L L /I0 I0 L L L H /I1 I1 L L H L /I2 I2 L L H H /I3 I3 L H L L /I4 I4 L H L H /I5 I5 L H H L /I6 I6 L H H H /I7 I7 H = HIGH voltage level; L = LOW voltage level; X = immaterial; Z = high impedance.
Pin Names Description U.L. HIGH/LOW --------- ---------------------------------------- ------------- S0 - S2 Select Inputs 0.5 / 0.375 /OE 3-State Output Enable Input (Active LOW) 0.5 / 0.375 I0 - I7 Multiplexer Inputs 0.5 / 0.375 Z Multiplexer Output 25 / 12.5 /Z Complementary Multiplexer Output 25 / 12.5
Symbol Parameter Typ Units
------ --------------------------------- ---- -----
Icc Power Supply Current, outputs ON 10 mA
Icc Power Supply Current, outputs OFF 10.5 mA
Conditions:
outputs ON -- In, Sn = 4.5 V; /OE = Gnd; Vcc = Max
outputs OFF -- /OE, In = 4.5 V; Vcc = Max
Symbol Parameter Min Typ Max Units ---------- --------------------------------- --- --- --- ----- tPLH Propagation Delay Sn to /Z -- 6.3 -- ns tPHL Propagation Delay Sn to /Z -- 6.2 -- ns tPLH Propagation Delay Sn to Z -- 8.1 -- ns tPHL Propagation Delay Sn to Z -- 7.9 -- ns tPLH Propagation Delay In to /Z -- 2.9 -- ns tPHL Propagation Delay In to /Z -- 2.8 -- ns tPLH Propagation Delay In to Z -- 4.7 -- ns tPHL Propagation Delay In to Z -- 4.5 -- ns tPZH, tPZL Output Enable Time /OE to /Z -- -- -- ns tPZH, tPZL Output Enable Time /OE to Z -- -- -- ns tPHZ, tPLZ Output Disable Time /OE to /Z (1) -- -- -- ns tPHZ, tPLZ Output Disable Time /OE to Z (1) -- -- -- ns (1) Disable times measured with CL = 5 pF.
Data sheet transcription as plain text
// ============================================================================ // f251.v — 54F/74F251 8-Input Multiplexer (With 3-State Outputs) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F251.txt (1980 Fairchild FAST Data Book, // pages 4-73 ... 4-75) — PRELIMINARY data sheet // // Selects one of eight data inputs under control of the Select inputs // S0, S1, S2. Both assertion (Z) and negation (Z_n) 3-state outputs are // provided. The Output Enable input (OE_n) is active LOW: when HIGH, both // Z and Z_n are forced to the high impedance state. // // Z = OE_n ? HiZ : (selected I_n) // Z_n = OE_n ? HiZ : ~(selected I_n) // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The sheet is // preliminary: only TYPICAL values are given for the data/select paths // (min/max columns blank), so those specparams carry the typ value only. // The Output Enable/Disable time rows (tPZH/tPZL/tPHZ/tPLZ) are printed // entirely BLANK on this data sheet — no values exist to transcribe, so no // OE_n specify path is given and the 3-state transitions propagate with // zero delay. (No timing invented; noted in the testbench and report.) // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f251 ( input wire i0, i1, i2, i3, // multiplexer inputs 0-3 input wire i4, i5, i6, i7, // multiplexer inputs 4-7 input wire s0, s1, s2, // select inputs input wire oe_n, // 3-state output enable (active LOW) output wire z, // multiplexer output output wire z_n // complementary multiplexer output ); // Selected data input (internal node), per the truth table: // S2 S1 S0 = binary index into I0..I7. wire d = s2 ? (s1 ? (s0 ? i7 : i6) : (s0 ? i5 : i4)) : (s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0)); assign z = oe_n ? 1'bz : d; assign z_n = oe_n ? 1'bz : ~d; specify // All values TYP only (preliminary data sheet; min/max columns // left blank), 54F/74F +25 C 5.0 V C_L = 15 pF. // Propagation delay Sn to Z_n (data sheet: typ 6.3 / 6.2 ns) specparam tlh_s_zn = 6.3; specparam thl_s_zn = 6.2; // Propagation delay Sn to Z (data sheet: typ 8.1 / 7.9 ns) specparam tlh_s_z = 8.1; specparam thl_s_z = 7.9; // Propagation delay In to Z_n (data sheet: typ 2.9 / 2.8 ns) specparam tlh_i_zn = 2.9; specparam thl_i_zn = 2.8; // Propagation delay In to Z (data sheet: typ 4.7 / 4.5 ns) specparam tlh_i_z = 4.7; specparam thl_i_z = 4.5; (s0, s1, s2 => z) = (tlh_s_z, thl_s_z); (s0, s1, s2 => z_n) = (tlh_s_zn, thl_s_zn); (i0, i1, i2, i3, i4, i5, i6, i7 => z) = (tlh_i_z, thl_i_z); (i0, i1, i2, i3, i4, i5, i6, i7 => z_n) = (tlh_i_zn, thl_i_zn); // Output Enable/Disable times OE_n to Z/Z_n (tPZH/tPZL/tPHZ/tPLZ): // rows printed BLANK on this preliminary data sheet, so no OE_n // path is specified — 3-state transitions propagate with zero // delay rather than with invented values. endspecify endmodule