// ============================================================================
// f251.v — 54F/74F251 8-Input Multiplexer (With 3-State Outputs)
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F251.txt (1980 Fairchild FAST Data Book,
//         pages 4-73 ... 4-75) — PRELIMINARY data sheet
//
// Selects one of eight data inputs under control of the Select inputs
// S0, S1, S2. Both assertion (Z) and negation (Z_n) 3-state outputs are
// provided. The Output Enable input (OE_n) is active LOW: when HIGH, both
// Z and Z_n are forced to the high impedance state.
//
//   Z   = OE_n ? HiZ :  (selected I_n)
//   Z_n = OE_n ? HiZ : ~(selected I_n)
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The sheet is
// preliminary: only TYPICAL values are given for the data/select paths
// (min/max columns blank), so those specparams carry the typ value only.
// The Output Enable/Disable time rows (tPZH/tPZL/tPHZ/tPLZ) are printed
// entirely BLANK on this data sheet — no values exist to transcribe, so no
// OE_n specify path is given and the 3-state transitions propagate with
// zero delay. (No timing invented; noted in the testbench and report.)
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f251 (
    input  wire i0, i1, i2, i3,   // multiplexer inputs 0-3
    input  wire i4, i5, i6, i7,   // multiplexer inputs 4-7
    input  wire s0, s1, s2,       // select inputs
    input  wire oe_n,             // 3-state output enable (active LOW)
    output wire z,                // multiplexer output
    output wire z_n               // complementary multiplexer output
);

    // Selected data input (internal node), per the truth table:
    // S2 S1 S0 = binary index into I0..I7.
    wire d = s2 ? (s1 ? (s0 ? i7 : i6) : (s0 ? i5 : i4))
                : (s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0));

    assign z   = oe_n ? 1'bz : d;
    assign z_n = oe_n ? 1'bz : ~d;

    specify
        // All values TYP only (preliminary data sheet; min/max columns
        // left blank), 54F/74F +25 C 5.0 V C_L = 15 pF.

        // Propagation delay Sn to Z_n (data sheet: typ 6.3 / 6.2 ns)
        specparam tlh_s_zn = 6.3;
        specparam thl_s_zn = 6.2;

        // Propagation delay Sn to Z (data sheet: typ 8.1 / 7.9 ns)
        specparam tlh_s_z = 8.1;
        specparam thl_s_z = 7.9;

        // Propagation delay In to Z_n (data sheet: typ 2.9 / 2.8 ns)
        specparam tlh_i_zn = 2.9;
        specparam thl_i_zn = 2.8;

        // Propagation delay In to Z (data sheet: typ 4.7 / 4.5 ns)
        specparam tlh_i_z = 4.7;
        specparam thl_i_z = 4.5;

        (s0, s1, s2 => z)   = (tlh_s_z,  thl_s_z);
        (s0, s1, s2 => z_n) = (tlh_s_zn, thl_s_zn);
        (i0, i1, i2, i3, i4, i5, i6, i7 => z)   = (tlh_i_z,  thl_i_z);
        (i0, i1, i2, i3, i4, i5, i6, i7 => z_n) = (tlh_i_zn, thl_i_zn);

        // Output Enable/Disable times OE_n to Z/Z_n (tPZH/tPZL/tPHZ/tPLZ):
        // rows printed BLANK on this preliminary data sheet, so no OE_n
        // path is specified — 3-state transitions propagate with zero
        // delay rather than with invented values.
    endspecify

endmodule