DESCRIPTION | CONNECTION DIAGRAM (20-pin DIP) | TRUTH TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F521 is an expandable 8-bit comparator. It compares two words of up to eight bits each and provides a LOW output when the two words match bit for bit. The expansion input /IA=B also serves as an active LOW enable input. o Compares Two 8-Bit Words in 6.5 ns Typ o Expandable to Any Word Length o 20-Pin Package
Pin Function Pin Function --- ------------------------ --- ------------------------ 1 /IA=B Expansion/Enable 20 Vcc 2 A0 Word A bit 0 19 /OA=B Identity output 3 B0 Word B bit 0 18 B7 Word B bit 7 4 A1 Word A bit 1 17 A7 Word A bit 7 5 B1 Word B bit 1 16 B6 Word B bit 6 6 A2 Word A bit 2 15 A6 Word A bit 6 7 B2 Word B bit 2 14 B5 Word B bit 5 8 A3 Word A bit 3 13 A5 Word A bit 5 9 B3 Word B bit 3 12 B4 Word B bit 4 10 GND 11 A4 Word A bit 4 The A and B inputs alternate along the package so that each bit pair (An, Bn) sits on adjacent pins.
Inputs Output -------------- ------ /IA=B A, B /OA=B ----- ------ ------ L A = B* L L A =/= B H H A = B* H H A =/= B H H = HIGH voltage level; L = LOW voltage level. *A0 = B0, A1 = B1, A2 = B2, etc.
Pin Names Description U.L. HIGH/LOW ---------- --------------------------------------- ------------- A0 - A7 Word A Inputs 0.5 / 0.375 B0 - B7 Word B Inputs 0.5 / 0.375 /IA=B Expansion or Enable Input (Active LOW) 0.5 / 0.375 /OA=B Identity Output (Active LOW) 25 / 12.5
Symbol Parameter Min Typ Max Units Conditions
------ -------------------- --- --- --- ----- ----------------
ICC Power Supply Current 21 32 mA Vcc = Max
All inputs HIGH
TA = +25 C 74F
Vcc = +5.0V TA/Vcc = Com
Symbol Parameter CL Min Typ Max Min Max Units
------ ----------------------------- ----- --- ---- --- --- ---- -----
tPLH Prop Delay An or Bn to /OA=B 50 pF 3.5 7.0 10.0 3.5 11.0 ns
tPHL Prop Delay An or Bn to /OA=B 50 pF 4.5 7.0 10.0 4.0 11.0 ns
tPLH Prop Delay /IA=B to /OA=B 50 pF 3.0 5.0 6.5 3.0 7.5 ns
tPHL Prop Delay /IA=B to /OA=B 50 pF 3.5 6.5 9.0 3.5 10.0 ns
Data sheet transcription as plain text
// ============================================================================ // f521.v — 54F/74F521 8-Bit Identity Comparator // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F521.txt (1985 Fairchild FAST Data Book, // pages 4-375 ... 4-377 — the 1980 data book carries the 'F521 in // its Section 3 selection guide only). // // Compares two 8-bit words A0-A7 and B0-B7 and drives the identity output // LOW when the words match bit for bit, provided the expansion input is // LOW. The expansion input also serves as an active LOW enable: with it // HIGH the output is HIGH regardless of the data inputs (data sheet truth // table). // // o_aeqb_n = i_aeqb_n | (A != B) // // Pin-name mapping: the data sheet pin names /IA=B and /OA=B contain // characters that are illegal in Verilog identifiers, so they appear here // as i_aeqb_n (expansion/enable input, pin 1) and o_aeqb_n (identity // output, pin 19); the _n suffix carries the active LOW sense. // // Timing values from the data sheet AC Characteristics table, T_A = +25 C, // V_CC = +5.0 V, C_L = 50 pF column, min:typ:max ns. The sheet's second // AC group, 74F over the commercial T_A/V_CC range, gives min/max only: // tPLH An or Bn to /OA=B 3.5 / 11.0 ns // tPHL An or Bn to /OA=B 4.0 / 11.0 ns // tPLH /IA=B to /OA=B 3.0 / 7.5 ns // tPHL /IA=B to /OA=B 3.5 / 10.0 ns // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f521 ( input wire a0, a1, a2, a3, // word A bits 0-3 input wire a4, a5, a6, a7, // word A bits 4-7 input wire b0, b1, b2, b3, // word B bits 0-3 input wire b4, b5, b6, b7, // word B bits 4-7 input wire i_aeqb_n, // /IA=B expansion/enable input (active LOW) output wire o_aeqb_n // /OA=B identity output (active LOW) ); // Bit-for-bit match of the two words (internal node) wire match = ~(a0 ^ b0) & ~(a1 ^ b1) & ~(a2 ^ b2) & ~(a3 ^ b3) & ~(a4 ^ b4) & ~(a5 ^ b5) & ~(a6 ^ b6) & ~(a7 ^ b7); assign o_aeqb_n = i_aeqb_n | ~match; specify // Propagation delay An or Bn to /OA=B (data sheet: tPLH 3.5/7.0/10.0, // tPHL 4.5/7.0/10.0 ns) specparam tlh_ab_o = 3.5:7.0:10.0; specparam thl_ab_o = 4.5:7.0:10.0; // Propagation delay /IA=B to /OA=B (data sheet: tPLH 3.0/5.0/6.5, // tPHL 3.5/6.5/9.0 ns) specparam tlh_i_o = 3.0:5.0:6.5; specparam thl_i_o = 3.5:6.5:9.0; (a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, b3, b4, b5, b6, b7 => o_aeqb_n) = (tlh_ab_o, thl_ab_o); (i_aeqb_n => o_aeqb_n) = (tlh_i_o, thl_i_o); endspecify endmodule