// ============================================================================
// f521.v — 54F/74F521 8-Bit Identity Comparator
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F521.txt (1985 Fairchild FAST Data Book,
//         pages 4-375 ... 4-377 — the 1980 data book carries the 'F521 in
//         its Section 3 selection guide only).
//
// Compares two 8-bit words A0-A7 and B0-B7 and drives the identity output
// LOW when the words match bit for bit, provided the expansion input is
// LOW. The expansion input also serves as an active LOW enable: with it
// HIGH the output is HIGH regardless of the data inputs (data sheet truth
// table).
//
//   o_aeqb_n = i_aeqb_n | (A != B)
//
// Pin-name mapping: the data sheet pin names /IA=B and /OA=B contain
// characters that are illegal in Verilog identifiers, so they appear here
// as i_aeqb_n (expansion/enable input, pin 1) and o_aeqb_n (identity
// output, pin 19); the _n suffix carries the active LOW sense.
//
// Timing values from the data sheet AC Characteristics table, T_A = +25 C,
// V_CC = +5.0 V, C_L = 50 pF column, min:typ:max ns. The sheet's second
// AC group, 74F over the commercial T_A/V_CC range, gives min/max only:
//   tPLH An or Bn to /OA=B  3.5 / 11.0 ns
//   tPHL An or Bn to /OA=B  4.0 / 11.0 ns
//   tPLH /IA=B to /OA=B     3.0 /  7.5 ns
//   tPHL /IA=B to /OA=B     3.5 / 10.0 ns
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f521 (
    input  wire a0, a1, a2, a3,   // word A bits 0-3
    input  wire a4, a5, a6, a7,   // word A bits 4-7
    input  wire b0, b1, b2, b3,   // word B bits 0-3
    input  wire b4, b5, b6, b7,   // word B bits 4-7
    input  wire i_aeqb_n,         // /IA=B expansion/enable input (active LOW)
    output wire o_aeqb_n          // /OA=B identity output (active LOW)
);

    // Bit-for-bit match of the two words (internal node)
    wire match = ~(a0 ^ b0) & ~(a1 ^ b1) & ~(a2 ^ b2) & ~(a3 ^ b3) &
                 ~(a4 ^ b4) & ~(a5 ^ b5) & ~(a6 ^ b6) & ~(a7 ^ b7);

    assign o_aeqb_n = i_aeqb_n | ~match;

    specify
        // Propagation delay An or Bn to /OA=B (data sheet: tPLH 3.5/7.0/10.0,
        // tPHL 4.5/7.0/10.0 ns)
        specparam tlh_ab_o = 3.5:7.0:10.0;
        specparam thl_ab_o = 4.5:7.0:10.0;

        // Propagation delay /IA=B to /OA=B (data sheet: tPLH 3.0/5.0/6.5,
        // tPHL 3.5/6.5/9.0 ns)
        specparam tlh_i_o = 3.0:5.0:6.5;
        specparam thl_i_o = 3.5:6.5:9.0;

        (a0, a1, a2, a3, a4, a5, a6, a7,
         b0, b1, b2, b3, b4, b5, b6, b7 => o_aeqb_n) = (tlh_ab_o, thl_ab_o);
        (i_aeqb_n => o_aeqb_n) = (tlh_i_o, thl_i_o);
    endspecify

endmodule