DESCRIPTION | CONNECTION DIAGRAM (20-pin DIP) | TRUTH TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F240, 'F241 and 'F244 are octal buffers and line drivers designed to be employed as memory address drivers, clock drivers and bus oriented transmitters/receivers which provide improved PC board density. o Hysteresis at inputs to improve noise margins o 3-state outputs drive bus lines or buffer memory address registers o Outputs sink 64 mA o 15 mA source current o Input clamp diodes limit high speed termination effects
Pin Function Pin Function --- ------------------------ --- ------------------------ 1 /OE1 Output Enable 1 20 Vcc 2 1D1 group 1 data input 19 /OE2 Output Enable 2 3 2O4 group 2 output 18 1O1 group 1 output 4 1D2 group 1 data input 17 2D4 group 2 data input 5 2O3 group 2 output 16 1O2 group 1 output 6 1D3 group 1 data input 15 2D3 group 2 data input 7 2O2 group 2 output 14 1O3 group 1 output 8 1D4 group 1 data input 13 2D2 group 2 data input 9 2O1 group 2 output 12 1O4 group 1 output 10 GND 11 2D1 group 2 data input /OE1 is the 3-State Output Enable for group 1 (active LOW); /OE2 is the 3-State Output Enable for group 2 (active LOW). The eight buffers are split into two independently enabled groups of four. Group 1 inputs enter on the left (pins 2, 4, 6, 8) and exit on the right (pins 18, 16, 14, 12); group 2 inputs enter on the right (pins 11, 13, 15, 17) and exit on the left (pins 9, 7, 5, 3).
/OE1, /OE2 D Output
---------- --- ------
L L H
L H L
H X Z
H = HIGH voltage level; L = LOW voltage level; X = immaterial;
Z = high impedance.
Pin Names Description U.L. HIGH/LOW
---------- ----------------------------------- -------------
/OE1, /OE2 3-State Output Enable (Active LOW) 0.5 / 0.625
Inputs 0.5 / 1.0
Outputs 75 / 40
Test conditions are keyed by number and listed below the table. Symbol Parameter Min Typ Max Units Cond --------- ---------------------------------- ---- --- ---- ----- ---- VOH Output HIGH Voltage 2.4 V (1) VOH Output HIGH Voltage 2.0 V (2) VOH Output HIGH Voltage 2.0 V (3) VOL Output LOW Voltage 0.55 V (4) VOL Output LOW Voltage 0.55 V (5) VT+ - VT- Hysteresis Voltage 0.2 0.4 V (6) IOS Output Short Circuit Current -100 -225 mA (7) ICC Power Supply Current, outputs HIGH 57 mA (8) ICC Power Supply Current, outputs LOW 64 mA (8) ICC Power Supply Current, outputs OFF 64 mA (8) Conditions (grade shown first where the data sheet gives one): (1) XM, XC: IOH = -3.0 mA, Vcc = Min, VIN = VIH or VIL (2) XM: IOH = -12 mA; VIH = 2.0 V, Vcc = Min, VIL = 0.5 V (3) XC: IOH = -15 mA; VIH = 2.0 V, Vcc = Min, VIL = 0.5 V (4) XM: IOL = 48 mA; VIN = VIH or VIL, Vcc = Min (5) XC: IOL = 64 mA; VIN = VIH or VIL, Vcc = Min (6) Vcc = Min (7) Vcc = Max, VOUT = 0 V (8) Vcc = Max
Symbol Parameter Min Typ Max Units ------ -------------------------------- --- --- --- ----- tPLH Propagation Delay Data to Output -- 4.5 -- ns tPHL Propagation Delay Data to Output -- 4.5 -- ns tPZH Output Enable Time -- 6.0 -- ns tPZL Output Enable Time -- 10 -- ns tPHZ Output Disable Time * -- 10 -- ns tPLZ Output Disable Time * -- 6.0 -- ns * Disable times measured with CL = 5.0 pF, RL = 90 ohms.
Data sheet transcription as plain text
// ============================================================================ // f240.v — 54F/74F240 Octal Buffer/Line Driver, Inverting (3-State Outputs) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F240.txt (1980 Fairchild FAST Data Book, // pages 4-68 ... 4-69; shared data sheet with 'F241/'F244, // preliminary) // // Eight inverting 3-state buffers in two independently enabled groups of // four. Group 1: 1D1..1D4 -> 1O1..1O4, enabled by OE1_n LOW. // Group 2: 2D1..2D4 -> 2O1..2O4, enabled by OE2_n LOW. // // Truth table (each buffer): OE_n=L, D=L -> H; OE_n=L, D=H -> L; // OE_n=H, D=X -> Z. // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), in ns. // The preliminary data sheet lists TYPICAL values only (Min/Max columns // left blank), so the specparams below are typ-only single values. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f240 ( input wire oe1_n, // output enable, group 1 (active LOW) input wire d1_1, d1_2, d1_3, d1_4, // group 1 data inputs output wire o1_1, o1_2, o1_3, o1_4, // group 1 outputs (inverting, 3-state) input wire oe2_n, // output enable, group 2 (active LOW) input wire d2_1, d2_2, d2_3, d2_4, // group 2 data inputs output wire o2_1, o2_2, o2_3, o2_4 // group 2 outputs (inverting, 3-state) ); assign o1_1 = oe1_n ? 1'bz : ~d1_1; assign o1_2 = oe1_n ? 1'bz : ~d1_2; assign o1_3 = oe1_n ? 1'bz : ~d1_3; assign o1_4 = oe1_n ? 1'bz : ~d1_4; assign o2_1 = oe2_n ? 1'bz : ~d2_1; assign o2_2 = oe2_n ? 1'bz : ~d2_2; assign o2_3 = oe2_n ? 1'bz : ~d2_3; assign o2_4 = oe2_n ? 1'bz : ~d2_4; specify // Data sheet AC Characteristics (preliminary: typ values only, // min/max columns blank), C_L = 15 pF; disable times measured with // C_L = 5.0 pF, R_L = 90 ohm: // tPLH = 4.5, tPHL = 4.5 (Propagation Delay Data to Output) // tPZH = 6.0, tPZL = 10 (Output Enable Time) // tPHZ = 10, tPLZ = 6.0 (Output Disable Time) specparam tlh = 4.5; // tPLH, data to output specparam thl = 4.5; // tPHL, data to output specparam tlz = 6.0; // tPLZ, output disable (0 -> Z) specparam tzh = 6.0; // tPZH, output enable (Z -> 1) specparam thz = 10.0; // tPHZ, output disable (1 -> Z) specparam tzl = 10.0; // tPZL, output enable (Z -> 0) (d1_1, oe1_n => o1_1) = (tlh, thl, tlz, tzh, thz, tzl); (d1_2, oe1_n => o1_2) = (tlh, thl, tlz, tzh, thz, tzl); (d1_3, oe1_n => o1_3) = (tlh, thl, tlz, tzh, thz, tzl); (d1_4, oe1_n => o1_4) = (tlh, thl, tlz, tzh, thz, tzl); (d2_1, oe2_n => o2_1) = (tlh, thl, tlz, tzh, thz, tzl); (d2_2, oe2_n => o2_2) = (tlh, thl, tlz, tzh, thz, tzl); (d2_3, oe2_n => o2_3) = (tlh, thl, tlz, tzh, thz, tzl); (d2_4, oe2_n => o2_4) = (tlh, thl, tlz, tzh, thz, tzl); endspecify endmodule