======================================================================== 74F240 OCTAL BUFFER/LINE DRIVER, INVERTING (WITH 3-STATE OUTPUTS) ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-68 ... 4-69 (shared data sheet with the 'F241 and 'F244) Status: PRELIMINARY -- page 4-68 carries a "Preliminary" watermark. Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F240, 'F241 and 'F244 are octal buffers and line drivers designed to be employed as memory address drivers, clock drivers and bus oriented transmitters/receivers which provide improved PC board density. o Hysteresis at inputs to improve noise margins o 3-state outputs drive bus lines or buffer memory address registers o Outputs sink 64 mA o 15 mA source current o Input clamp diodes limit high speed termination effects CONNECTION DIAGRAM (20-pin DIP) ------------------------------- Pin Function Pin Function --- ------------------------ --- ------------------------ 1 /OE1 Output Enable 1 20 Vcc 2 1D1 group 1 data input 19 /OE2 Output Enable 2 3 2O4 group 2 output 18 1O1 group 1 output 4 1D2 group 1 data input 17 2D4 group 2 data input 5 2O3 group 2 output 16 1O2 group 1 output 6 1D3 group 1 data input 15 2D3 group 2 data input 7 2O2 group 2 output 14 1O3 group 1 output 8 1D4 group 1 data input 13 2D2 group 2 data input 9 2O1 group 2 output 12 1O4 group 1 output 10 GND 11 2D1 group 2 data input /OE1 is the 3-State Output Enable for group 1 (active LOW); /OE2 is the 3-State Output Enable for group 2 (active LOW). The eight buffers are split into two independently enabled groups of four. Group 1 inputs enter on the left (pins 2, 4, 6, 8) and exit on the right (pins 18, 16, 14, 12); group 2 inputs enter on the right (pins 11, 13, 15, 17) and exit on the left (pins 9, 7, 5, 3). TRUTH TABLE ----------- /OE1, /OE2 D Output ---------- --- ------ L L H L H L H X Z H = HIGH voltage level; L = LOW voltage level; X = immaterial; Z = high impedance. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW ---------- ----------------------------------- ------------- /OE1, /OE2 3-State Output Enable (Active LOW) 0.5 / 0.625 Inputs 0.5 / 1.0 Outputs 75 / 40 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Test conditions are keyed by number and listed below the table. Symbol Parameter Min Typ Max Units Cond --------- ---------------------------------- ---- --- ---- ----- ---- VOH Output HIGH Voltage 2.4 V (1) VOH Output HIGH Voltage 2.0 V (2) VOH Output HIGH Voltage 2.0 V (3) VOL Output LOW Voltage 0.55 V (4) VOL Output LOW Voltage 0.55 V (5) VT+ - VT- Hysteresis Voltage 0.2 0.4 V (6) IOS Output Short Circuit Current -100 -225 mA (7) ICC Power Supply Current, outputs HIGH 57 mA (8) ICC Power Supply Current, outputs LOW 64 mA (8) ICC Power Supply Current, outputs OFF 64 mA (8) Conditions (grade shown first where the data sheet gives one): (1) XM, XC: IOH = -3.0 mA, Vcc = Min, VIN = VIH or VIL (2) XM: IOH = -12 mA; VIH = 2.0 V, Vcc = Min, VIL = 0.5 V (3) XC: IOH = -15 mA; VIH = 2.0 V, Vcc = Min, VIL = 0.5 V (4) XM: IOL = 48 mA; VIN = VIH or VIL, Vcc = Min (5) XC: IOL = 64 mA; VIN = VIH or VIL, Vcc = Min (6) Vcc = Min (7) Vcc = Max, VOUT = 0 V (8) Vcc = Max AC CHARACTERISTICS ------------------ Symbol Parameter Min Typ Max Units ------ -------------------------------- --- --- --- ----- tPLH Propagation Delay Data to Output -- 4.5 -- ns tPHL Propagation Delay Data to Output -- 4.5 -- ns tPZH Output Enable Time -- 6.0 -- ns tPZL Output Enable Time -- 10 -- ns tPHZ Output Disable Time * -- 10 -- ns tPLZ Output Disable Time * -- 6.0 -- ns * Disable times measured with CL = 5.0 pF, RL = 90 ohms.