74F04

HEX INVERTER

Family: Fairchild FAST (Advanced Schottky TTL)
Source: 1980 Fairchild FAST Data Book, page 4-5
Status: Released data sheet
Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C

DESCRIPTION

The 74F04 contains six independent inverters in a 14-pin package.

Logic function (each inverter):   Z = /A

CONNECTION DIAGRAM (14-pin DIP)

Pin  Function             Pin  Function
---  -------------------  ---  -------------------
  1  A1  input 1           14  Vcc
  2  Z1  output 1          13  A6  input 6
  3  A2  input 2           12  Z6  output 6
  4  Z2  output 2          11  A5  input 5
  5  A3  input 3           10  Z5  output 5
  6  Z3  output 3           9  A4  input 4
  7  GND                    8  Z4  output 4

TRUTH TABLE

 A    Z
---  ---
 L    H
 H    L

H = HIGH voltage level;  L = LOW voltage level.

INPUT LOADING / FAN-OUT

Pin Names    Description    U.L. HIGH/LOW
-----------  -------------  -------------
             Inputs         0.5 / 0.375
             Outputs        25 / 12.5

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE

Symbol  Parameter             Min  Typ   Max  Units  Conditions
------  --------------------  ---  ---  ----  -----  ---------------------
ICCH    Power Supply Current             4.2  mA     VIN = Gnd, Vcc = Max
ICCL    Power Supply Current            15.3  mA     VIN = Open, Vcc = Max

AC CHARACTERISTICS

Symbol  Parameter        CL     Min  Typ  Max  Units
------  ---------------  -----  ---  ---  ---  -----
tPLH    Propagation Dly  15 pF  1.5  2.7  3.8  ns
tPLH    Propagation Dly  50 pF  2.0   --  6.0  ns
tPHL    Propagation Dly  15 pF  1.5  2.5  3.5  ns
tPHL    Propagation Dly  50 pF  2.0   --  5.5  ns

Data sheet transcription as plain text

VERILOG MODEL

// ============================================================================
// f04.v — 54F/74F04 Hex Inverter
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F04.txt (1980 Fairchild FAST Data Book, page 4-5)
//
// Logic function (each inverter): Z = ~A
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns.
// The sheet's second row, C_L = 50 pF, gives min/max only:
//   A to Z   tPLH 2.0 / 6.0   tPHL 2.0 / 5.5 ns
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f04 (
    input  wire a1,         // inverter 1 input
    output wire z1,         // inverter 1 output
    input  wire a2,         // inverter 2 input
    output wire z2,         // inverter 2 output
    input  wire a3,         // inverter 3 input
    output wire z3,         // inverter 3 output
    input  wire a4,         // inverter 4 input
    output wire z4,         // inverter 4 output
    input  wire a5,         // inverter 5 input
    output wire z5,         // inverter 5 output
    input  wire a6,         // inverter 6 input
    output wire z6          // inverter 6 output
);

    assign z1 = ~a1;
    assign z2 = ~a2;
    assign z3 = ~a3;
    assign z4 = ~a4;
    assign z5 = ~a5;
    assign z6 = ~a6;

    specify
        // Propagation delay, A to Z (data sheet: tPLH 1.5/2.7/3.8,
        // tPHL 1.5/2.5/3.5 ns)
        specparam tlh = 1.5:2.7:3.8;
        specparam thl = 1.5:2.5:3.5;

        (a1 => z1) = (tlh, thl);
        (a2 => z2) = (tlh, thl);
        (a3 => z3) = (tlh, thl);
        (a4 => z4) = (tlh, thl);
        (a5 => z5) = (tlh, thl);
        (a6 => z6) = (tlh, thl);
    endspecify

endmodule

f04.v as plain text