// ============================================================================
// f04.v — 54F/74F04 Hex Inverter
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F04.txt (1980 Fairchild FAST Data Book, page 4-5)
//
// Logic function (each inverter): Z = ~A
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns.
// The sheet's second row, C_L = 50 pF, gives min/max only:
//   A to Z   tPLH 2.0 / 6.0   tPHL 2.0 / 5.5 ns
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f04 (
    input  wire a1,         // inverter 1 input
    output wire z1,         // inverter 1 output
    input  wire a2,         // inverter 2 input
    output wire z2,         // inverter 2 output
    input  wire a3,         // inverter 3 input
    output wire z3,         // inverter 3 output
    input  wire a4,         // inverter 4 input
    output wire z4,         // inverter 4 output
    input  wire a5,         // inverter 5 input
    output wire z5,         // inverter 5 output
    input  wire a6,         // inverter 6 input
    output wire z6          // inverter 6 output
);

    assign z1 = ~a1;
    assign z2 = ~a2;
    assign z3 = ~a3;
    assign z4 = ~a4;
    assign z5 = ~a5;
    assign z6 = ~a6;

    specify
        // Propagation delay, A to Z (data sheet: tPLH 1.5/2.7/3.8,
        // tPHL 1.5/2.5/3.5 ns)
        specparam tlh = 1.5:2.7:3.8;
        specparam thl = 1.5:2.5:3.5;

        (a1 => z1) = (tlh, thl);
        (a2 => z2) = (tlh, thl);
        (a3 => z3) = (tlh, thl);
        (a4 => z4) = (tlh, thl);
        (a5 => z5) = (tlh, thl);
        (a6 => z6) = (tlh, thl);
    endspecify

endmodule