// ============================================================================
// f64.v — 54F/74F64 4-2-3-2-Input AND-OR-Invert Gate
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F64.txt (1980 Fairchild FAST Data Book, page 4-11)
//         (data sheet page marked "Preliminary")
//
// Logic function: Z = ~((A & B & C & D) | (E & F) | (G & H & I) | (J & K))
// Four AND groups of 4, 2, 3 and 2 inputs respectively are OR-ed and
// inverted: Z is LOW when any AND group has all of its inputs HIGH.
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns.
// The sheet's second row, C_L = 50 pF, gives min/max only:
//   any input to Z   tPLH 2.0 / 7.0   tPHL 2.0 / 5.5 ns
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f64 (
    input  wire a, b, c, d, // 4-input AND group
    input  wire e, f,       // 2-input AND group
    input  wire g, h, i,    // 3-input AND group
    input  wire j, k,       // 2-input AND group
    output wire z           // output
);

    assign z = ~((a & b & c & d) | (e & f) | (g & h & i) | (j & k));

    specify
        // Propagation delay, any input to Z (data sheet: tPLH 1.5/3.6/4.8,
        // tPHL 1.5/2.8/3.8 ns)
        specparam tlh = 1.5:3.6:4.8;
        specparam thl = 1.5:2.8:3.8;

        (a, b, c, d, e, f, g, h, i, j, k => z) = (tlh, thl);
    endspecify

endmodule