// ============================================================================
// f353.v — 54F/74F353 Dual 4-Input Multiplexer, Inverting
//          (With 3-State Outputs)
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F353.txt (1980 Fairchild FAST Data Book,
//         pages 4-97 ... 4-99) — PRELIMINARY data sheet
//
// Two 4-input multiplexers with common Select inputs S0, S1 and individual
// active-LOW Output Enables (OE_na, OE_nb), presenting the selected data
// in INVERTED form. A HIGH on an Output Enable forces the corresponding
// output to the high impedance state.
//
//   Z_na = OE_na ? HiZ : ~(selected I_na)
//   Z_nb = OE_nb ? HiZ : ~(selected I_nb)
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The sheet is
// preliminary: only TYPICAL values are given for the data/select paths
// (min/max columns blank), so those specparams carry the typ value only.
// The Output Enable/Disable time rows (tPZH/tPZL/tPHZ/tPLZ) are printed
// entirely BLANK on this data sheet — no values exist to transcribe, so no
// OE_n specify path is given and the 3-state transitions propagate with
// zero delay. (No timing invented; noted in the testbench and report.)
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f353 (
    input  wire s0, s1,                 // common select inputs
    input  wire oe_na,                  // side A output enable (active LOW)
    input  wire i0a, i1a, i2a, i3a,     // side A data inputs 0-3
    output wire za_n,                   // side A inverted 3-state output
    input  wire oe_nb,                  // side B output enable (active LOW)
    input  wire i0b, i1b, i2b, i3b,     // side B data inputs 0-3
    output wire zb_n                    // side B inverted 3-state output
);

    // Selected data inputs (internal nodes), per the truth table:
    // S1 S0 = binary index into I0..I3 of each side.
    wire da = s1 ? (s0 ? i3a : i2a) : (s0 ? i1a : i0a);
    wire db = s1 ? (s0 ? i3b : i2b) : (s0 ? i1b : i0b);

    assign za_n = oe_na ? 1'bz : ~da;
    assign zb_n = oe_nb ? 1'bz : ~db;

    specify
        // All values TYP only (preliminary data sheet; min/max columns
        // left blank), 54F/74F +25 C 5.0 V C_L = 15 pF.

        // Propagation delay Sn to Z_n (data sheet: typ 6.3 / 6.2 ns)
        specparam tlh_s = 6.3;
        specparam thl_s = 6.2;

        // Propagation delay In to Z_n (data sheet: typ 2.9 / 2.8 ns)
        specparam tlh_i = 2.9;
        specparam thl_i = 2.8;

        (s0, s1 => za_n) = (tlh_s, thl_s);
        (s0, s1 => zb_n) = (tlh_s, thl_s);
        (i0a, i1a, i2a, i3a => za_n) = (tlh_i, thl_i);
        (i0b, i1b, i2b, i3b => zb_n) = (tlh_i, thl_i);

        // Output Enable/Disable times OE_n to Z_n (tPZH/tPZL/tPHZ/tPLZ):
        // rows printed BLANK on this preliminary data sheet, so no OE_n
        // path is specified — 3-state transitions propagate with zero
        // delay rather than with invented values.
    endspecify

endmodule