// ============================================================================
// f283.v — 54F/74F283 4-Bit Binary Full Adder (With Fast Carry)
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F283.txt (1980 Fairchild FAST Data Book,
//         pages 4-87 ... 4-90) — PRELIMINARY data sheet
//
// Function (data sheet functional description):
//   2^0(a0 + b0 + c0) + 2^1(a1 + b1) + 2^2(a2 + b2) + 2^3(a3 + b3)
//       = s0 + 2*s1 + 4*s2 + 8*s3 + 16*c4
// i.e. {c4, s3, s2, s1, s0} = a + b + c0. The same binary add realizes the
// data sheet's active-HIGH (positive logic) and active-LOW (negative logic)
// interpretations.
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF).
// NOTE: the preliminary data sheet lists TYPICAL values only; the Min/Max
// columns were left blank, so each specparam carries the typ value alone.
// The sheet gives one figure for "A_n or B_n to S_n" and one for "A_n or B_n
// to C4"; they are applied here to every output functionally dependent on
// the operand input (an operand bit also feeds the higher sum bits and C4
// through the internal carry lookahead). The carry path (C0 to C4, 4.7 ns)
// is roughly half the carry-to-sum path — the point of the fast carry.
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f283 (
    input  wire a0,         // A operand input 0
    input  wire a1,         // A operand input 1
    input  wire a2,         // A operand input 2
    input  wire a3,         // A operand input 3
    input  wire b0,         // B operand input 0
    input  wire b1,         // B operand input 1
    input  wire b2,         // B operand input 2
    input  wire b3,         // B operand input 3
    input  wire c0,         // carry input
    output wire s0,         // sum output 0
    output wire s1,         // sum output 1
    output wire s2,         // sum output 2
    output wire s3,         // sum output 3
    output wire c4          // carry output
);

    wire [4:0] total = {1'b0, a3, a2, a1, a0}
                     + {1'b0, b3, b2, b1, b0}
                     + c0;

    assign s0 = total[0];
    assign s1 = total[1];
    assign s2 = total[2];
    assign s3 = total[3];
    assign c4 = total[4];

    specify
        // Propagation delay C0 to S_n (data sheet: tPLH 8.2, tPHL 7.5 ns —
        // typ only, preliminary sheet, min/max blank)
        specparam tlh_c_s  = 8.2;
        specparam thl_c_s  = 7.5;

        // Propagation delay A_n or B_n to S_n (data sheet: tPLH 8.5,
        // tPHL 8.5 ns — typ only, preliminary sheet, min/max blank)
        specparam tlh_ab_s = 8.5;
        specparam thl_ab_s = 8.5;

        // Propagation delay C0 to C4 (data sheet: tPLH 4.7, tPHL 4.7 ns —
        // typ only, preliminary sheet, min/max blank)
        specparam tlh_c_c4  = 4.7;
        specparam thl_c_c4  = 4.7;

        // Propagation delay A_n or B_n to C4 (data sheet: tPLH 4.7,
        // tPHL 4.7 ns — typ only, preliminary sheet, min/max blank)
        specparam tlh_ab_c4 = 4.7;
        specparam thl_ab_c4 = 4.7;

        // Carry input paths
        (c0 => s0) = (tlh_c_s, thl_c_s);
        (c0 => s1) = (tlh_c_s, thl_c_s);
        (c0 => s2) = (tlh_c_s, thl_c_s);
        (c0 => s3) = (tlh_c_s, thl_c_s);
        (c0 => c4) = (tlh_c_c4, thl_c_c4);

        // Operand input paths: each a_n/b_n feeds its own sum bit and,
        // via the lookahead carry, every higher sum bit and C4.
        (a0, b0 => s0) = (tlh_ab_s, thl_ab_s);
        (a0, b0, a1, b1 => s1) = (tlh_ab_s, thl_ab_s);
        (a0, b0, a1, b1, a2, b2 => s2) = (tlh_ab_s, thl_ab_s);
        (a0, b0, a1, b1, a2, b2, a3, b3 => s3) = (tlh_ab_s, thl_ab_s);
        (a0, b0, a1, b1, a2, b2, a3, b3 => c4) = (tlh_ab_c4, thl_ab_c4);
    endspecify

endmodule