// ============================================================================
// f253.v — 54F/74F253 Dual 4-Input Multiplexer (With 3-State Outputs)
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F253.txt (1980 Fairchild FAST Data Book,
//         pages 4-76 ... 4-78)
//
// Two 4-input multiplexers with common Select inputs S0, S1 and individual
// active-LOW Output Enables (OE_na, OE_nb). A HIGH on an Output Enable
// forces the corresponding output to the high impedance state. Outputs
// are non-inverting:
//
//   Za = OE_na ? HiZ : selected I_na
//   Zb = OE_nb ? HiZ : selected I_nb
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns.
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f253 (
    input  wire s0, s1,                 // common select inputs
    input  wire oe_na,                  // side A output enable (active LOW)
    input  wire i0a, i1a, i2a, i3a,     // side A data inputs 0-3
    output wire za,                     // side A 3-state output
    input  wire oe_nb,                  // side B output enable (active LOW)
    input  wire i0b, i1b, i2b, i3b,     // side B data inputs 0-3
    output wire zb                      // side B 3-state output
);

    // Selected data inputs (internal nodes), per the truth table:
    // S1 S0 = binary index into I0..I3 of each side.
    wire da = s1 ? (s0 ? i3a : i2a) : (s0 ? i1a : i0a);
    wire db = s1 ? (s0 ? i3b : i2b) : (s0 ? i1b : i0b);

    assign za = oe_na ? 1'bz : da;
    assign zb = oe_nb ? 1'bz : db;

    specify
        // Propagation delay In to Zn (data sheet: tPLH 2.0/4.4/6.0,
        // tPHL 2.0/4.4/6.0 ns)
        specparam tlh_i = 2.0:4.4:6.0;
        specparam thl_i = 2.0:4.4:6.0;

        // Propagation delay Sn to Zn (data sheet: tPLH 4.0/9.5/13,
        // tPHL 3.0/8.0/10 ns)
        specparam tlh_s = 4.0:9.5:13.0;
        specparam thl_s = 3.0:8.0:10.0;

        // Output enable time OE_n to Zn (data sheet: tPZH 2.0/5.3/7.0,
        // tPZL 2.0/6.5/8.0 ns)
        specparam tzh = 2.0:5.3:7.0;
        specparam tzl = 2.0:6.5:8.0;

        // Output disable time OE_n to Zn, C_L = 5 pF (data sheet:
        // tPHZ 2.0/4.3/6.0, tPLZ 2.0/4.0/6.0 ns)
        specparam thz = 2.0:4.3:6.0;
        specparam tlz = 2.0:4.0:6.0;

        // 6-delay form, IEEE order (0->1, 1->0, 0->Z, Z->1, 1->Z, Z->0)
        (oe_na, i0a, i1a, i2a, i3a => za) = (tlh_i, thl_i, tlz, tzh, thz, tzl);
        (oe_nb, i0b, i1b, i2b, i3b => zb) = (tlh_i, thl_i, tlz, tzh, thz, tzl);
        (s0, s1 => za) = (tlh_s, thl_s);
        (s0, s1 => zb) = (tlh_s, thl_s);
    endspecify

endmodule