// ============================================================================
// f157.v — 54F/74F157 Quad 2-Input Multiplexer
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F157.txt (1980 Fairchild FAST Data Book,
//         pages 4-22 ... 4-24)
//
// Four 2-input multiplexers with a common Select input (S) and a common
// active-LOW Enable (e_n). S LOW selects the I0 (source 0) inputs, S HIGH
// selects the I1 (source 1) inputs. The outputs present data in the true
// (non-inverted) form. When e_n is HIGH, all outputs are forced LOW
// regardless of all other inputs.
//
//   zn = ~e_n & (s ? i1n : i0n)
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns.
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f157 (
    input  wire s,                  // select input (common)
    input  wire e_n,                // enable input (active LOW)
    input  wire i0a, i1a,           // source 0/1 data inputs, bit a
    output wire za,                 // output a
    input  wire i0b, i1b,           // source 0/1 data inputs, bit b
    output wire zb,                 // output b
    input  wire i0c, i1c,           // source 0/1 data inputs, bit c
    output wire zc,                 // output c
    input  wire i0d, i1d,           // source 0/1 data inputs, bit d
    output wire zd                  // output d
);

    assign za = ~e_n & (s ? i1a : i0a);
    assign zb = ~e_n & (s ? i1b : i0b);
    assign zc = ~e_n & (s ? i1c : i0c);
    assign zd = ~e_n & (s ? i1d : i0d);

    specify
        // Propagation delay S to Z_n (data sheet: 4.0/8.5/13,
        // 3.0/6.0/9.0 ns)
        specparam tlh_s_z = 4.0:8.5:13;
        specparam thl_s_z = 3.0:6.0:9.0;

        // Propagation delay E_n to Z_n (data sheet: 2.0/6.5/8.0,
        // 2.0/4.5/7.0 ns)
        specparam tlh_e_z = 2.0:6.5:8.0;
        specparam thl_e_z = 2.0:4.5:7.0;

        // Propagation delay I_n to Z_n (data sheet: 2.0/4.5/6.0,
        // 2.0/3.5/4.5 ns)
        specparam tlh_i_z = 2.0:4.5:6.0;
        specparam thl_i_z = 2.0:3.5:4.5;

        (s => za) = (tlh_s_z, thl_s_z);
        (s => zb) = (tlh_s_z, thl_s_z);
        (s => zc) = (tlh_s_z, thl_s_z);
        (s => zd) = (tlh_s_z, thl_s_z);
        (e_n => za) = (tlh_e_z, thl_e_z);
        (e_n => zb) = (tlh_e_z, thl_e_z);
        (e_n => zc) = (tlh_e_z, thl_e_z);
        (e_n => zd) = (tlh_e_z, thl_e_z);
        (i0a, i1a => za) = (tlh_i_z, thl_i_z);
        (i0b, i1b => zb) = (tlh_i_z, thl_i_z);
        (i0c, i1c => zc) = (tlh_i_z, thl_i_z);
        (i0d, i1d => zd) = (tlh_i_z, thl_i_z);
    endspecify

endmodule