// ============================================================================
// f138.v — 54F/74F138 1-of-8 Decoder/Demultiplexer
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F138.txt (1985 Fairchild FAST Data Book,
//         pages 4-45 ... 4-48 — the 1980 data book carries the 'F138 in
//         its Section 3 selection guide only, page 3-15).
//
// Three binary weighted address inputs (A0, A1, A2) select one of eight
// mutually exclusive active LOW outputs (/O0 - /O7). Three Enable inputs,
// two active LOW (/E1, /E2) and one active HIGH (E3), gate the decoder: all
// outputs are HIGH unless /E1 and /E2 are LOW and E3 is HIGH. Either
// active-LOW Enable input can serve as the data input of an 8-output
// demultiplexer, with the remaining Enable inputs used as strobes.
//
//   E   = ~e1_n & ~e2_n & e3
//   /On = ~(E & ({a2, a1, a0} == n))
//
// Timing values from the data sheet AC Characteristics table, T_A = +25 C,
// V_CC = +5.0 V, C_L = 50 pF column, min:typ:max ns. The sheet's second
// column, 74F over the commercial T_A/V_CC range, gives min/max only:
//
//   An to /On           tPLH 3.5 / 8.5   tPHL 4.0 / 9.0 ns
//   /E1 or /E2 to /On   tPLH 3.5 / 8.0   tPHL 3.0 / 7.5 ns
//   E3 to /On           tPLH 4.0 / 9.0   tPHL 3.5 / 8.5 ns
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f138 (
    input  wire a0, a1, a2,             // binary weighted address inputs
    input  wire e1_n, e2_n,             // enable inputs (active LOW)
    input  wire e3,                     // enable input (active HIGH)
    output wire o0_n, o1_n, o2_n, o3_n, // outputs 0-3 (active LOW)
    output wire o4_n, o5_n, o6_n, o7_n  // outputs 4-7 (active LOW)
);

    // Internal enable term: all outputs are HIGH unless /E1 and /E2 are LOW
    // and E3 is HIGH.
    wire e = ~e1_n & ~e2_n & e3;

    assign o0_n = ~(e & ~a2 & ~a1 & ~a0);
    assign o1_n = ~(e & ~a2 & ~a1 &  a0);
    assign o2_n = ~(e & ~a2 &  a1 & ~a0);
    assign o3_n = ~(e & ~a2 &  a1 &  a0);
    assign o4_n = ~(e &  a2 & ~a1 & ~a0);
    assign o5_n = ~(e &  a2 & ~a1 &  a0);
    assign o6_n = ~(e &  a2 &  a1 & ~a0);
    assign o7_n = ~(e &  a2 &  a1 &  a0);

    specify
        // T_A = +25 C, V_CC = +5.0 V, C_L = 50 pF, min:typ:max ns.

        // Propagation delay An to /On
        // (data sheet: tPLH 3.5/5.6/7.5, tPHL 4.0/6.1/8.0)
        specparam tlh_a = 3.5:5.6:7.5;
        specparam thl_a = 4.0:6.1:8.0;

        // Propagation delay /E1 or /E2 to /On
        // (data sheet: tPLH 3.5/5.4/7.0, tPHL 3.0/5.3/7.0)
        specparam tlh_e = 3.5:5.4:7.0;
        specparam thl_e = 3.0:5.3:7.0;

        // Propagation delay E3 to /On
        // (data sheet: tPLH 4.0/6.2/8.0, tPHL 3.5/5.6/7.5)
        specparam tlh_e3 = 4.0:6.2:8.0;
        specparam thl_e3 = 3.5:5.6:7.5;

        (a0, a1, a2 => o0_n) = (tlh_a, thl_a);
        (a0, a1, a2 => o1_n) = (tlh_a, thl_a);
        (a0, a1, a2 => o2_n) = (tlh_a, thl_a);
        (a0, a1, a2 => o3_n) = (tlh_a, thl_a);
        (a0, a1, a2 => o4_n) = (tlh_a, thl_a);
        (a0, a1, a2 => o5_n) = (tlh_a, thl_a);
        (a0, a1, a2 => o6_n) = (tlh_a, thl_a);
        (a0, a1, a2 => o7_n) = (tlh_a, thl_a);

        (e1_n, e2_n => o0_n) = (tlh_e, thl_e);
        (e1_n, e2_n => o1_n) = (tlh_e, thl_e);
        (e1_n, e2_n => o2_n) = (tlh_e, thl_e);
        (e1_n, e2_n => o3_n) = (tlh_e, thl_e);
        (e1_n, e2_n => o4_n) = (tlh_e, thl_e);
        (e1_n, e2_n => o5_n) = (tlh_e, thl_e);
        (e1_n, e2_n => o6_n) = (tlh_e, thl_e);
        (e1_n, e2_n => o7_n) = (tlh_e, thl_e);

        (e3 => o0_n) = (tlh_e3, thl_e3);
        (e3 => o1_n) = (tlh_e3, thl_e3);
        (e3 => o2_n) = (tlh_e3, thl_e3);
        (e3 => o3_n) = (tlh_e3, thl_e3);
        (e3 => o4_n) = (tlh_e3, thl_e3);
        (e3 => o5_n) = (tlh_e3, thl_e3);
        (e3 => o6_n) = (tlh_e3, thl_e3);
        (e3 => o7_n) = (tlh_e3, thl_e3);
    endspecify

endmodule