======================================================================== 74F398 QUAD 2-PORT REGISTER (TRUE AND COMPLEMENT OUTPUTS) ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1985 Fairchild FAST Data Book, pages 4-268 ... 4-270 (shared data sheet with the 'F399, see 54F74F399.txt). The 1980 data book carries the 'F398 in its Section 3 selection guide only (page 3-20, description and logic symbol). Status: Released data sheet Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F398 and 'F399 are the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flip-flops on the rising edge of the clock. The 'F399 is the 16-pin version of the 'F398, with only the Q outputs of the flip-flops available. o Select Inputs from Two Data Sources o Fully Positive Edge-Triggered Operation o Both True and Complement Outputs -- 'F398 FUNCTIONAL DESCRIPTION ---------------------- The 'F398 and 'F399 are high-speed quad 2-port registers. They select four bits of data from either of two sources (Ports) under control of a common Select input (S). The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input (CP). The 4-bit D-type output register is fully edge-triggered. The Data inputs (I0x, I1x) and Select input (S) must be stable only a setup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation. The 'F398 has both Q and /Q outputs. CONNECTION DIAGRAM (20-pin DIP) ------------------------------- Pin Function Pin Function --- -------------------------- --- -------------------------- 1 S Common Select 20 Vcc 2 Qa True output a 19 Qd True output d 3 /Qa Complement output a 18 /Qd Complement output d 4 I0a Source 0 data input a 17 I0d Source 0 data input d 5 I1a Source 1 data input a 16 I1d Source 1 data input d 6 I1b Source 1 data input b 15 I1c Source 1 data input c 7 I0b Source 0 data input b 14 I0c Source 0 data input c 8 /Qb Complement output b 13 /Qc Complement output c 9 Qb True output b 12 Qc True output c 10 GND 11 CP Clock Pulse CP is active on the rising edge of the clock, and drives all four flip-flops in parallel. FUNCTION TABLE -------------- Inputs Outputs ----------- ----------- S I0 I1 Q /Q - -- -- --- --- l l X L H l h X H L h X l L H h X h H L H = HIGH voltage level; L = LOW voltage level; X = immaterial. h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition. l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW ---------- -------------------------------------- ------------- S Common Select Input 0.5 / 0.375 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 I0a - I0d Data Inputs from Source 0 0.5 / 0.375 I1a - I1d Data Inputs from Source 1 0.5 / 0.375 Qa - Qd Register True Outputs 25 / 12.5 /Qa - /Qd Register Complementary Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ---------------------- ICC Power Supply Current 25 38 mA Vcc = Max, VIN = Gnd, CP = rising edge AC CHARACTERISTICS ------------------ TA = +25 C 74F Vcc = +5.0V TA/Vcc = Com Symbol Parameter CL Min Typ Max Min Max Units ------ ----------------------------- ----- --- --- --- --- ---- ----- fmax Input Clock Frequency -- 100 140 -- 100 -- MHz tPLH Prop Delay CP to Q or /Q 50 pF 3.0 5.7 7.5 3.0 8.5 ns tPHL Prop Delay CP to Q or /Q 50 pF 3.0 6.8 9.5 3.0 10.0 ns AC OPERATING REQUIREMENTS ------------------------- TA = +25 C 74F Vcc = +5.0V TA/Vcc = Com Symbol Parameter Min Typ Max Min Max Units ------ ------------------------------------- --- --- --- --- --- ----- ts (H) Setup Time, HIGH -- In to CP 3.0 -- -- 3.0 -- ns ts (L) Setup Time, LOW -- In to CP 3.0 -- -- 3.0 -- ns th (H) Hold Time, HIGH -- In to CP 1.0 -- -- 1.0 -- ns th (L) Hold Time, LOW -- In to CP 1.0 -- -- 1.0 -- ns ts (H) Setup Time, HIGH -- S to CP 7.5 -- -- 8.5 -- ns ts (L) Setup Time, LOW -- S to CP 7.5 -- -- 8.5 -- ns th (H) Hold Time, HIGH -- S to CP 0 -- -- 0 -- ns th (L) Hold Time, LOW -- S to CP 0 -- -- 0 -- ns tw (H) CP Pulse Width, HIGH 4.0 -- -- 4.0 -- ns tw (L) CP Pulse Width, LOW 5.0 -- -- 5.0 -- ns