======================================================================== 74F373 OCTAL TRANSPARENT LATCH (WITH 3-STATE OUTPUTS) ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-100 ... 4-102 Status: Released data sheet Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (/OE) is LOW. When /OE is HIGH the bus output is in the high impedance state. o EIGHT LATCHES IN A SINGLE PACKAGE o 3-STATE OUTPUTS FOR BUS INTERFACING FUNCTIONAL DESCRIPTION ---------------------- The 'F373 contains eight D-type latches with 3-state output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state buffers are controlled by the Output Enable (/OE) input. When /OE is LOW, the buffers are in the bi-state mode. When /OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. CONNECTION DIAGRAM (20-pin DIP) ------------------------------- Pin Function Pin Function --- ------------------------------- --- ------------------------------- 1 /OE Output Enable (active LOW) 20 Vcc 2 O0 Latch output 0 19 O7 Latch output 7 3 D0 Data input 0 18 D7 Data input 7 4 D1 Data input 1 17 D6 Data input 6 5 O1 Latch output 1 16 O6 Latch output 6 6 O2 Latch output 2 15 O5 Latch output 5 7 D2 Data input 2 14 D5 Data input 5 8 D3 Data input 3 13 D4 Data input 4 9 O3 Latch output 3 12 O4 Latch output 4 10 GND 11 LE Latch Enable (active HIGH) INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW --------- -------------------------------- ------------- D0 - D7 Data Inputs 0.5 / 0.375 LE Latch Enable Input (Active HIGH) 0.5 / 0.375 /OE Output Enable Input (Active LOW) 0.5 / 0.375 O0 - O7 3-State Latch Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Conditions for all rows: Vcc = Max, /OE = 4.5 V; Dn, LE = Gnd. Symbol Parameter Min Typ Max Units ------ -------------------------------------- --- --- --- ----- ICC Power Supply Current (All Outputs OFF) 35 55 mA AC CHARACTERISTICS ------------------ Symbol Parameter Min Typ Max Units ------ -------------------------- --- --- --- ----- tPLH Propagation Delay Dn to On 2.0 4.3 6.5 ns tPHL Propagation Delay Dn to On 1.0 2.7 4.5 ns tPLH Propagation Delay LE to On 4.0 9.2 13 ns tPHL Propagation Delay LE to On 2.0 4.2 6.5 ns tPZH Output Enable Time 3.0 6.8 11 ns tPZL Output Enable Time 3.0 6.0 10 ns tPHZ Output Disable Time (1) 3.0 5.7 9.0 ns tPLZ Output Disable Time (1) 3.0 6.2 9.0 ns (1) Disable times measured with CL = 5.0 pF. AC OPERATING REQUIREMENTS ------------------------- Symbol Parameter Min Typ Max Units ------ ---------------------------- --- --- --- ----- ts (H) Setup Time, HIGH -- Dn to LE 2.0 -- -- ns ts (L) Setup Time, LOW -- Dn to LE 2.0 -- -- ns th (H) Hold Time, HIGH -- Dn to LE 3.0 -- -- ns th (L) Hold Time, LOW -- Dn to LE 3.0 -- -- ns tw (H) LE Pulse Width HIGH 6.0 -- -- ns