======================================================================== 74F257 QUAD 2-INPUT MULTIPLEXER (WITH 3-STATE OUTPUTS) ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-79 ... 4-81 Status: Released data sheet Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F257 is a quad 2-input multiplexer with 3-state outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four outputs present the selected data in true (non-inverted) form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (/OE) input, allowing the outputs to interface directly with bus oriented systems. o Multiplexer expansion by tying outputs together o Non-inverting 3-state outputs o Input clamp diodes limit high speed termination effects FUNCTIONAL DESCRIPTION ---------------------- The 'F257 selects four bits of data from two sources under control of a Common Data Select input. When the Select input is LOW, the I0x inputs are selected; when Select is HIGH, the I1x inputs are selected. The data on the selected inputs appears at the outputs in true (non-inverted) form. The device is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. Za = /OE * ( I1a*S + I0a*/S ) Zb = /OE * ( I1b*S + I0b*/S ) Zc = /OE * ( I1c*S + I0c*/S ) Zd = /OE * ( I1d*S + I0d*/S ) When the Output Enable input (/OE) is HIGH, the outputs are forced to a high impedance OFF state. If the outputs are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure the Output Enable signals to 3-state devices whose outputs are tied together are designed so there is no overlap. CONNECTION DIAGRAM (16-pin DIP) ------------------------------- Pin Function Pin Function --- ----------------------------- --- -------------------------- 1 S Common Data Select input 16 Vcc 2 I0a Source 0, bit a 15 /OE 3-State Output Enable 3 I1a Source 1, bit a 14 I0c Source 0, bit c 4 Za Output a 13 I1c Source 1, bit c 5 I0b Source 0, bit b 12 Zc Output c 6 I1b Source 1, bit b 11 I0d Source 0, bit d 7 Zb Output b 10 I1d Source 1, bit d 8 GND 9 Zd Output d The 3-State Output Enable input /OE (pin 15) is active LOW. Pin-compatible with the 'F157; pin 15 becomes a 3-state Output Enable. TRUTH TABLE (each section) -------------------------- /OE S I0 I1 Z --- - -- -- --- H X X X (Z) L H X L L L H X H H L L L X L L L H X H H = HIGH voltage level; L = LOW voltage level; X = immaterial; (Z) = high impedance. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW --------- ---------------------------------------- ------------- S Common Data Select Input 0.5 / 0.375 /OE 3-State Output Enable Input (Active LOW) 0.5 / 0.375 I0a - I0d Data Inputs from Source 0 0.5 / 0.375 I1a - I1d Data Inputs from Source 1 0.5 / 0.375 Za - Zd Multiplexer Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Symbol Parameter Min Typ Max Units ------ ---------------------------------- --- ---- --- ----- Icc Power Supply Current, outputs HIGH 9.0 15 mA Icc Power Supply Current, outputs LOW 14.5 22 mA Icc Power Supply Current, outputs OFF 15 23 mA Conditions: outputs HIGH -- Vcc = Max; S, I1x = 4.5 V; /OE, I0x = Gnd outputs LOW -- Vcc = Max; I1x = 4.5 V; /OE, I0x, S = Gnd outputs OFF -- Vcc = Max; S, I0x = Gnd; /OE, I1x = 4.5 V AC CHARACTERISTICS ------------------ Symbol Parameter Min Typ Max Units ------ -------------------------- --- --- --- ----- tPLH Propagation Delay In to Zn 2.0 4.0 6.0 ns tPHL Propagation Delay In to Zn 2.0 3.5 4.5 ns tPLH Propagation Delay S to Zn 4.0 10 13 ns tPHL Propagation Delay S to Zn 3.0 7.5 9.0 ns tPZH Output Enable Time 2.0 5.0 7.0 ns tPZL Output Enable Time 2.0 5.5 7.0 ns tPHZ Output Disable Time* 2.0 4.0 6.0 ns tPLZ Output Disable Time* 2.0 4.0 6.0 ns *CL = 5 pF