======================================================================== 74F192 UP/DOWN DECADE COUNTER (WITH SEPARATE UP/DOWN CLOCKS) ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-57 ... 4-60 Status: PRELIMINARY -- page 4-57 carries a "Preliminary" watermark. Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F192 is an up/down BCD decade (8421) counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stage without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuits to be used as programmable counters. Both the Parallel Load (/PL) and the Master Reset (MR) inputs asynchronously override the clocks. FUNCTIONAL DESCRIPTION ---------------------- The 'F192 and 'F193 are asynchronously presettable decade and 4-bit binary synchronous up/down (reversible) counters. The operating modes of the 'F192 decade counter and the 'F193 binary counter are identical, with the only difference being the count sequences as noted in the State Diagram. Each circuit contains four edge-triggered flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up and count down operations. A LOW-to-HIGH transition on the CP input to each flip-flop causes the output to change state. Synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up input will advance the count by one; a similar transition on the Count Down input will decrease the count by one. While counting with one clock input, the other should be held HIGH. Otherwise, the circuit will either count by twos or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either Clock input is LOW. The Terminal Count Up (/TCU) and Terminal Count Down (/TCD) outputs are normally HIGH. When a circuit has reached the maximum count state (9 for the 'F192, 15 for the 'F193), the next HIGH-to-LOW transition of the Count Up Clock will cause /TCU to go LOW. /TCU will stay LOW until CPU goes HIGH again, thus effectively repeating the Count Up Clock, but delayed by two gate delays. Similarly, the /TCD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. Since the /TC outputs repeat the clock waveforms, they can be used as the clock input signals to the next higher order circuit in a multistage counter. /TCU = Q0 * Q3 * /CPU /TCD = /Q0 * /Q1 * /Q2 * /Q3 * /CPD Each circuit has an asynchronous parallel load capability permitting the counter to be preset. When the Parallel Load (/PL) and the Master Reset (MR) inputs are LOW, information present on the Parallel Data input (P0 - P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. A HIGH signal on the Master Reset input will disable the preset gates, override both Clock inputs, and latch each Q output in the LOW state. If one of the Clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that Clock will be interpreted as a legitimate signal and will be counted. CONNECTION DIAGRAM (16-pin DIP) ------------------------------- Pin Function Pin Function --- -------------------------- --- --------------------------------- 1 P1 Parallel data input 1 16 Vcc 2 Q1 Flip-flop output 1 15 P0 Parallel data input 0 3 Q0 Flip-flop output 0 14 MR Master Reset 4 CPD Count Down Clock 13 /TCD Terminal Count Down / Borrow 5 CPU Count Up Clock 12 /TCU Terminal Count Up / Carry 6 Q2 Flip-flop output 2 11 /PL Parallel Load input 7 Q3 Flip-flop output 3 10 P2 Parallel data input 2 8 GND 9 P3 Parallel data input 3 MODE SELECT TABLE ----------------- MR /PL CPU CPD Mode --- --- --- --- --------------------- H X X X Reset (Asynchronous) L L X X Preset (Asynchronous) L H H H No Change L H ^ H Count Up L H H ^ Count Down H = HIGH voltage level; L = LOW voltage level; X = immaterial; ^ = LOW-to-HIGH transition. STATE DIAGRAM ------------- The diagram draws all sixteen states around a square: 0-1-2-3-4 across the top, 4-5-6-7-8 down the right, 8-9-10-11-12 across the bottom and 12-13-14-15 up the left. Decade sequence 0 <-> 9, with the wrap 9 -> 0 counting up (solid diagonal) and 0 -> 9 counting down (dashed diagonal). Illegal states 10 - 15 recover into the legal sequence: counting UP the paths are 10 -> 11 -> 6, 12 -> 13 -> 4 and 14 -> 15 -> 2; counting DOWN the illegal states chain downward 15 -> 14 -> 13 -> 12 -> 11 -> 10 -> 9, entering the legal sequence at 9. (Solid arrows = count up, dashed arrows = count down.) INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW --------- ------------------------------------------------ ------------- CPU Count Up Clock Input (Active Rising Edge) 0.5 / 0.75 CPD Count Down Clock Input (Active Rising Edge) 0.5 / 0.75 MR Asynchronous Master Reset Input (Active HIGH) 0.5 / 0.375 /PL Asynchronous Parallel Load Input (Active LOW) 0.5 / 0.375 P0 - P3 Parallel Data Inputs 0.5 / 0.375 Q0 - Q3 Flip-flop Outputs 25 / 12.5 /TCD Terminal Count Down (Borrow) Output (Active LOW) 25 / 12.5 /TCU Terminal Count Up (Carry) Output (Active LOW) 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- (unless otherwise specified) Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ---------- ICC Power Supply Current 35 mA Vcc = Max AC CHARACTERISTICS ------------------ Symbol Parameter Min Typ Max Units ------ ---------------------------------- --- --- --- ----- fmax Maximum Count Frequency 90 130 -- MHz tPLH Propagation Dly CPU to /TCU -- 5.0 -- ns tPHL Propagation Dly CPU to /TCU -- 4.5 -- ns tPLH Propagation Dly CPD to /TCD -- 5.0 -- ns tPHL Propagation Dly CPD to /TCD -- 4.5 -- ns tPLH Propagation Dly CPU or CPD to Qn -- 4.5 -- ns tPHL Propagation Dly CPU or CPD to Qn -- 5.5 -- ns tPLH Propagation Dly Pn to Qn -- 3.6 -- ns tPHL Propagation Dly Pn to Qn -- 6.3 -- ns tPLH Propagation Dly /PL to Qn -- 5.7 -- ns tPHL Propagation Dly /PL to Qn -- 6.2 -- ns tPHL Propagation Dly MR to Qn -- 5.2 -- ns tPLH Propagation Dly MR to /TCU -- 7.5 -- ns tPHL Propagation Dly MR to /TCD -- 5.5 -- ns tPLH Propagation Dly /PL to /TCU -- 8.5 -- ns tPHL Propagation Dly /PL to /TCD -- 8.5 -- ns tPLH Propagation Dly Pn to /TCU or /TCD -- 8.5 -- ns tPHL Propagation Dly Pn to /TCU or /TCD -- 6.7 -- ns AC OPERATING REQUIREMENTS ------------------------- Symbol Parameter Min Typ Max Units ------ ---------------------------------- --- --- --- ----- ts (H) Setup Time, HIGH -- Pn to /PL 5.0 -- -- ns ts (L) Setup Time, LOW -- Pn to /PL 5.0 -- -- ns th (H) Hold Time, HIGH -- Pn to /PL 3.0 -- -- ns th (L) Hold Time, LOW -- Pn to /PL 3.0 -- -- ns tw (L) /PL Pulse Width LOW 5.0 -- -- ns tw (L) CPU Pulse Width LOW 5.5 -- -- ns tw (L) CPD Pulse Width LOW 5.5 -- -- ns tw (H) MR Pulse Width HIGH 5.5 -- -- ns trec Recovery Time -- /PL to CPU or CPD 6.0 -- -- ns trec Recovery Time -- MR to CPU or CPD 6.0 -- -- ns