======================================================================== 74F190 UP/DOWN DECADE COUNTER (WITH PRESET AND RIPPLE CLOCK) ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-48 ... 4-51 Status: PRELIMINARY -- page 4-48 carries a "Preliminary" watermark. Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F190 is a reversible BCD (8421) decade counter featuring synchronous counting and asynchronous presetting. The preset feature allows the 'F190 to be used in programmable dividers. The Count Enable input, the Terminal Count output and the Ripple Clock output make possible a variety of methods of implementing multistage counters. In the counting modes, state changes are initiated by the rising edge of the clock. o High speed -- 70 MHz typical count frequency o Synchronous counting o Asynchronous parallel load o Cascadable FUNCTIONAL DESCRIPTION ---------------------- The 'F190 is a synchronous up/down BCD decade counter containing four edge-triggered flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations. It has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (/PL) input is LOW, information present on the Parallel Data inputs (P0 - P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the /CE input inhibits counting. When /CE is LOW, internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the /U/D input signal, as indicated in the Mode Select Table. /CE and /U/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches 9 in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until /U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (/RC) output. The /RC output is normally HIGH. When /CE is LOW and TC is HIGH, the /RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage counters. For a discussion and illustrations of the various methods of implementing multistage counters, please see the 'F191 data sheet. CONNECTION DIAGRAM (16-pin DIP) ------------------------------- Pin Function Pin Function --- --------------------------- --- -------------------------------- 1 P1 Parallel data input 1 16 Vcc 2 Q1 Flip-flop output 1 15 P0 Parallel data input 0 3 Q0 Flip-flop output 0 14 CP Clock Pulse 4 /CE Count Enable 13 /RC Ripple Clock output 5 /U/D Up/Down Count Control 12 TC Terminal Count output 6 Q2 Flip-flop output 2 11 /PL Parallel Load input 7 Q3 Flip-flop output 3 10 P2 Parallel data input 2 8 GND 9 P3 Parallel data input 3 MODE SELECT TABLE ----------------- /PL /CE /U/D CP Mode --- --- ---- --- --------------------- H L L ^ Count Up H L H ^ Count Down L X X X Preset (Asynchronous) H H X X No Change (Hold) H = HIGH voltage level; L = LOW voltage level; X = immaterial; ^ = LOW-to-HIGH transition. /RC TRUTH TABLE --------------- /CE TC(1) CP /RC --- ----- ------- ------- L H (pulse) (pulse) H X X H X L X H (1) TC is generated internally. STATE DIAGRAM ------------- The counter runs 0 <-> 9 in the BCD sequence, with wrap 9 -> 0 counting up and 0 -> 9 counting down. Illegal states 10 - 15 recover into the legal sequence: counting UP, the paths are 10 -> 11 -> 6, 12 -> 13 -> 4 and 14 -> 15 -> 2; counting DOWN, the illegal states chain downward 15 -> 14 -> 13 -> 12 -> 11 -> 10 -> 9, entering the legal sequence at 9. (Solid arrows = count up, dashed arrows = count down.) INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW --------- --------------------------------------------- ------------- /CE Count Enable Input (Active LOW) 0.5 / 1.125 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 P0 - P3 Parallel Data Inputs 0.5 / 0.375 /PL Asynchronous Parallel Load Input (Active LOW) 0.5 / 0.375 /U/D Up/Down Count Control Input 0.5 / 0.375 Q0 - Q3 Flip-flop Outputs 25 / 12.5 /RC Ripple Clock Output (Active LOW) 25 / 12.5 TC Terminal Count Output (Active HIGH) 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) -------------------------------------------------------------------------------- Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ---------- ICC Power Supply Current 38 mA Vcc = Max AC CHARACTERISTICS ------------------ Symbol Parameter Min Typ Max Units ------ ------------------------------------ --- --- --- ----- fmax Maximum Count Frequency 90 130 -- MHz tPLH Propagation Dly CP to Qn -- 4.5 -- ns tPHL Propagation Dly CP to Qn -- 5.5 -- ns tPLH Propagation Dly CP to TC -- 6.5 -- ns tPHL Propagation Dly CP to TC -- 8.5 -- ns tPLH Propagation Dly CP to /RC -- 4.5 -- ns tPHL Propagation Dly CP to /RC -- 4.0 -- ns tPLH Propagation Dly /CE to /RC -- 3.6 -- ns tPHL Propagation Dly /CE to /RC -- 3.5 -- ns tPLH Propagation Dly /U/D to /RC -- 10 -- ns tPHL Propagation Dly /U/D to /RC -- 8.0 -- ns tPLH Propagation Dly /U/D to TC -- 5.0 -- ns tPHL Propagation Dly /U/D to TC -- 5.5 -- ns tPLH Propagation Dly Pn to Qn -- 3.6 -- ns tPHL Propagation Dly Pn to Qn -- 6.3 -- ns tPLH Propagation Dly /PL to Qn, /RC or TC -- 5.7 -- ns tPHL Propagation Dly /PL to Qn, /RC or TC -- 6.2 -- ns AC OPERATING REQUIREMENTS ------------------------- Symbol Parameter Min Typ Max Units ------ ----------------------------- --- --- --- ----- ts (H) Setup Time, HIGH -- Pn to /PL 5.0 -- -- ns ts (L) Setup Time, LOW -- Pn to /PL 5.0 -- -- ns th (H) Hold Time, HIGH -- Pn to /PL 3.0 -- -- ns th (L) Hold Time, LOW -- Pn to /PL 3.0 -- -- ns ts (L) Setup Time LOW -- /CE to CP 10 -- -- ns th (L) Hold Time LOW -- /CE to CP 0 -- -- ns tw (L) /PL Pulse Width LOW 5.0 -- -- ns tw (L) CP Pulse Width LOW 5.5 -- -- ns trec Recovery Time -- /PL to CP 6.0 -- -- ns