DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (40-pin DIP) | MODE SELECT TABLE | TABLE 1 'F557 ROUNDING INPUTS | TABLE 2 'F558 ROUNDING INPUTS | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS
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Family: Fairchild FAST (Advanced Schottky TTL)
Source: 1985 Fairchild FAST Data Book, pages 4-438 ... 4-444
(shared data sheet with the 'F557, see 54F74F557.txt). The 1980
data book carries the 'F558 in its Section 3 selection guide
only (page 3-35, description and logic symbol).
Status: PRELIMINARY -- page 4-438 carries a "Preliminary" watermark.
Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C
The 'F557 and 'F558 are high-speed combinatorial arrays that multiply two 8-bit unsigned or signed twos complement numbers and provide the 16-bit unsigned or signed product. Each input operand X and Y has a mode control input that determines whether the number is treated as signed or unsigned. Additional inputs, Rs and Ru for the 'F558 or R for the 'F557, allow the addition of a bit for rounding to the best signed or unsigned fractional 8-bit result. For expansion during signed or mixed multiplication, both the true and complement outputs of the most significant bit are available. The 'F557 has output latches that store the results when /LE is HIGH. Both devices have 3-state outputs for bus applications. o Unsigned, Signed or Mixed Multiplication o Full 16-Bit Product Outputs o MSB Complement Output for Signed Expansion o Rounding Inputs for Fractional 8-Bit Product
The 'F557 and 'F558 multipliers are 8x8 combinatorial logic arrays
capable of multiplying numbers in unsigned, signed twos complement or
mixed notation. Each 8-bit input operand X and Y has an associated mode
control which determines whether the array treats the number as signed
or unsigned. If the mode control XM or YM is HIGH, the operand is
treated as a twos complement number with the most significant bit having
a negative weight; if the mode control is LOW, the operand is treated as
an unsigned number.
The multipliers provide all sixteen product bits generated by the
multiplication. For expansion during signed or mixed multiplication, the
most significant product bit has both true and complement available.
Therefore, an adder may be used as a subtractor in many applications and
the need for SSI circuits is eliminated.
The 'F557 has latches that store the product for pipelined operations.
When /LE is HIGH the latches are transparent and their outputs change
with their inputs. When /LE is LOW the latches are in the storage mode
and new data cannot enter.
The 3-state output buffers are controlled by the active LOW Output
Enable /OE input. When /OE is LOW, the outputs are active; when /OE is
HIGH, the outputs are in a high impedance (High Z) state. Several
multipliers can be connected on a common bus or used in a pipeline
system for multiplications in higher speed systems.
Rounding
~~~~~~~~
The 16-bit product can be truncated to eight bits by using the rounding
input(s) to add one in either the 2^7 adder for unsigned numbers or in
the 2^6 adder for signed numbers. The 'F558 has separate rounding inputs
Rs and Ru for signed or unsigned numbers, respectively. The 'F557 has a
single rounding input R and develops the proper rounding by internally
combining R with XM and YM as follows:
Ru = /XM * /YM * R = unsigned rounding input to 2^7 adder
Rs = (XM +/- YM) R = signed rounding input to 2^6 adder
Rounding input levels and results for the various modes are shown in
Tables 1 and 2. Figure a shows how Rs and Ru would normally be used for
rounding signed and unsigned fractional multipliers.
Signed Expansion
~~~~~~~~~~~~~~~~
The most significant product bit has both true and complement outputs
available. When building larger signed multipliers the partial products,
except at the lower stages, are signed numbers. These unsigned and
signed partial products must be added to give the correct signed
product. For example, to obtain the correct signed product when using
MSI adders, the carry from the previous adder stage must be added to the
sum of the two negative most significant partial product bits. The
result of this addition must be a positive sum and a negative carry
(borrow). The equations are:
S = A + B + C
C0 = A*B + B*/C + /C*A
where C is the Carry In and A and B the sign bits of the two partial
products.
An adder produces the equations:
S = A + B + C
C0 = A*B + B*C + C*A
Therefore, if the inversion of A and B is used, then the adder produces
the inversion of the negative carry since
A*B + B*/C + /C*A = /(/A*/B + /B*C + /A*C)
and the sum remains the same.
Pin Function Pin Function --- ------------------------ --- ------------------------ 1 X0 Multiplicand bit 0 40 XM Multiplicand sign 2 X1 Multiplicand bit 1 39 S0 Product bit 0 3 X2 Multiplicand bit 2 38 S1 Product bit 1 4 X3 Multiplicand bit 3 37 S2 Product bit 2 5 X4 Multiplicand bit 4 36 S3 Product bit 3 6 X5 Multiplicand bit 5 35 S4 Product bit 4 7 X6 Multiplicand bit 6 34 S5 Product bit 5 8 X7 Multiplicand bit 7 33 S6 Product bit 6 9 Rs Signed rounding 32 S7 Product bit 7 10 Vcc 31 S8 Product bit 8 11 Ru Unsigned rounding 30 GND 12 Y0 Multiplier bit 0 29 S9 Product bit 9 13 Y1 Multiplier bit 1 28 S10 Product bit 10 14 Y2 Multiplier bit 2 27 S11 Product bit 11 15 Y3 Multiplier bit 3 26 S12 Product bit 12 16 Y4 Multiplier bit 4 25 S13 Product bit 13 17 Y5 Multiplier bit 5 24 S14 Product bit 14 18 Y6 Multiplier bit 6 23 S15 Product bit 15 19 Y7 Multiplier bit 7 22 /S15 MSB complement 20 YM Multiplier sign 21 /OE Output Enable The pin assignments printed on the connection diagram are for the 'F558; on the 'F557 pin 9 is R (in place of Rs) and pin 11 is /LE (in place of Ru). Vcc and GND are on pins 10 and 30 rather than at the corners of the package.
Input Data Mode Control Inputs
Operating ------------------------------ -------------------
Mode X0-X7 Y0-Y7 XM YM
---------- ---------------- -------------- ---- ----
Unsigned Unsigned Unsigned L L
Mixed Unsigned Twos Complement L H
Twos Complement Unsigned H L
Signed Twos Complement Twos Complement H H
H = HIGH voltage level; L = LOW voltage level.
Inputs Adds ------------- --------- XM YM R 2^7 2^6 -- -- -- --- --- L L H Yes No L H H No Yes H L H No Yes H H H No Yes X X L No No H = HIGH voltage level; L = LOW voltage level; X = immaterial.
Inputs Adds Normally Used With --------- --------- ------------------------ Ru Rs 2^7 2^6 XM YM -- -- --- --- ----------- -- L L No No X X L H No Yes XM + YM = H H L Yes No L L H H Yes Yes * * *Most rounding applications require a HIGH level for Ru or Rs, but not both. H = HIGH voltage level; L = LOW voltage level; X = immaterial.
Pin Names Description U.L. HIGH/LOW
---------- ----------------------------------------- -------------
X0 - X7 Multiplicand Inputs 0.5 / 0.5
Y0 - Y7 Multiplier Inputs 0.5 / 0.5
XM Multiplicand Sign Control Input 0.5 / 0.5
YM Multiplier Sign Control Input 0.5 / 0.5
R Rounding Input ('F557) 0.5 / 0.5
Rs Signed Number Rounding Input ('F558) 0.5 / 0.5
Ru Unsigned Number Rounding Input ('F558) 0.5 / 0.5
/LE Latch Enable Input (Active LOW) ('F557) 0.5 / 0.5
/OE 3-State Output Enable Input (Active LOW) 0.5 / 0.5
S0 - S15 Product Outputs 50 / 12.5
/S15 MSB Complement Output 50 / 12.5
Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ---------- ICC Power Supply Current 200 280 mA Vcc = Max
At TA = +25 C, Vcc = +5.0 V, CL = 50 pF.
Symbol Parameter Min Typ Max Units
------ --------------------------------- --- --- ---- -----
tPLH Prop Delay Xn or Yn to Sn, /S15 -- -- 70.0 ns
tPHL Prop Delay Xn or Yn to Sn, /S15 -- -- 70.0 ns
tPZH Output Enable Time /OE to Sn -- -- 14.0 ns
or /S15
tPZL Output Enable Time /OE to Sn -- -- 14.0 ns
or /S15
tPHZ Output Disable Time /OE to Sn -- -- 21.0 ns
or /S15
tPLZ Output Disable Time /OE to Sn -- -- 14.0 ns
or /S15
Data sheet transcription as plain text
No model for this device yet — only the data sheet transcription above.