DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | TRUTH TABLE (each section) | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F258 is a quad 2-input multiplexer with 3-state outputs. Four bits of data from two sources can be selected using a common data select input. The four outputs present the selected data in the complement (inverted) form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (/OE) input, allowing the outputs to interface directly with bus oriented systems. o Multiplexer expansion by tying outputs together o Inverting 3-state outputs
The 'F258 is a quad 2-input multiplexer with 3-state outputs. It
selects four bits of data from two sources under control of a common
Select input (S). When the Select input is LOW, the I0x inputs are
selected; when Select is HIGH, the I1x inputs are selected. The data
on the selected inputs appears at the outputs in inverted form. The
'F258 is the logic implementation of a 4-pole, 2-position switch where
the position of the switch is determined by the logic levels supplied
to the Select input.
/Za = /OE * ( I1a*S + I0a*/S ) /Zb = /OE * ( I1b*S + I0b*/S )
/Zc = /OE * ( I1c*S + I0c*/S ) /Zd = /OE * ( I1d*S + I0d*/S )
When the Output Enable input (/OE) is HIGH, the outputs are forced to a
high impedance OFF state. If the outputs of the 3-state devices are
tied together, all but one device must be in the high impedance state
to avoid high currents that would exceed the maximum ratings.
Designers should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so there is no overlap.
Pin Function Pin Function --- ----------------------------- --- -------------------------- 1 S Common Data Select input 16 Vcc 2 I0a Source 0, bit a 15 /OE 3-State Output Enable 3 I1a Source 1, bit a 14 I0c Source 0, bit c 4 /Za Inverting output a 13 I1c Source 1, bit c 5 I0b Source 0, bit b 12 /Zc Inverting output c 6 I1b Source 1, bit b 11 I0d Source 0, bit d 7 /Zb Inverting output b 10 I1d Source 1, bit d 8 GND 9 /Zd Inverting output d The 3-State Output Enable input /OE (pin 15) is active LOW. Pin-for-pin identical to the 'F257 except the outputs are inverted.
/OE S I0 I1 /Z --- - -- -- -- H X X X Z L H X L H L H X H L L L L X H L L H X L H = HIGH voltage level; L = LOW voltage level; X = immaterial; Z = high impedance.
Pin Names Description U.L. HIGH/LOW --------- ---------------------------------------- ------------- S Common Data Select Input 0.5 / 0.375 /OE 3-State Output Enable Input (Active LOW) 0.5 / 0.375 I0a - I0d Data Inputs from Source 0 0.5 / 0.375 I1a - I1d Data Inputs from Source 1 0.5 / 0.375 /Za - /Zd Inverting Data Outputs 25 / 12.5
Symbol Parameter Min Typ Max Units
------ ---------------------------------- --- ---- --- -----
Icc Power Supply Current, outputs HIGH 5.8 mA
Icc Power Supply Current, outputs LOW 14 mA
Icc Power Supply Current, outputs OFF 16.8 mA
Conditions:
outputs HIGH -- Vcc = Max; S, I1x = 4.5 V; /OE, I0x = Gnd
outputs LOW -- Vcc = Max; I1x = 4.5 V; /OE, I0x, S = Gnd
outputs OFF -- Vcc = Max; S, I0x = Gnd; /OE, I1x = 4.5 V
Symbol Parameter Min Typ Max Units ---------- --------------------------- --- --- --- ----- tPLH Propagation Delay In to /Zn -- 2.9 -- ns tPHL Propagation Delay In to /Zn -- 2.8 -- ns tPLH Propagation Delay S to /Zn -- 6.3 -- ns tPHL Propagation Delay S to /Zn -- 6.2 -- ns tPZH, tPZL Output Enable Time* -- -- -- ns tPHZ, tPLZ Output Disable Time* -- -- -- ns *CL = 5 pF
Data sheet transcription as plain text
// ============================================================================ // f258.v — 54F/74F258 Quad 2-Input Multiplexer, Inverting // (With 3-State Outputs) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F258.txt (1980 Fairchild FAST Data Book, // pages 4-82 ... 4-84) — PRELIMINARY data sheet // // Four 2-input multiplexers with a common Data Select input S and a common // active-LOW 3-state Output Enable (OE_n). When S is LOW the I0x inputs // are selected, when HIGH the I1x inputs. Data appears at the outputs in // INVERTED form. A HIGH on OE_n forces all outputs to the high impedance // state. // // Z_nx = OE_n ? HiZ : ~(S ? I1x : I0x) // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The sheet is // preliminary: only TYPICAL values are given for the data/select paths // (min/max columns blank), so those specparams carry the typ value only. // The Output Enable/Disable time rows (tPZH/tPZL/tPHZ/tPLZ) are printed // entirely BLANK on this data sheet — no values exist to transcribe, so no // OE_n specify path is given and the 3-state transitions propagate with // zero delay. (No timing invented; noted in the testbench and report.) // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f258 ( input wire s, // common data select input input wire oe_n, // 3-state output enable (active LOW) input wire i0a, i1a, // source 0/1 data inputs, bit a output wire za_n, // inverting output a input wire i0b, i1b, // source 0/1 data inputs, bit b output wire zb_n, // inverting output b input wire i0c, i1c, // source 0/1 data inputs, bit c output wire zc_n, // inverting output c input wire i0d, i1d, // source 0/1 data inputs, bit d output wire zd_n // inverting output d ); assign za_n = oe_n ? 1'bz : ~(s ? i1a : i0a); assign zb_n = oe_n ? 1'bz : ~(s ? i1b : i0b); assign zc_n = oe_n ? 1'bz : ~(s ? i1c : i0c); assign zd_n = oe_n ? 1'bz : ~(s ? i1d : i0d); specify // All values TYP only (preliminary data sheet; min/max columns // left blank), 54F/74F +25 C 5.0 V C_L = 15 pF. // Propagation delay In to Z_n (data sheet: typ 2.9 / 2.8 ns) specparam tlh_i = 2.9; specparam thl_i = 2.8; // Propagation delay S to Z_n (data sheet: typ 6.3 / 6.2 ns) specparam tlh_s = 6.3; specparam thl_s = 6.2; (i0a, i1a => za_n) = (tlh_i, thl_i); (i0b, i1b => zb_n) = (tlh_i, thl_i); (i0c, i1c => zc_n) = (tlh_i, thl_i); (i0d, i1d => zd_n) = (tlh_i, thl_i); (s => za_n) = (tlh_s, thl_s); (s => zb_n) = (tlh_s, thl_s); (s => zc_n) = (tlh_s, thl_s); (s => zd_n) = (tlh_s, thl_s); // Output Enable/Disable times OE_n to Z_n (tPZH/tPZL/tPHZ/tPLZ): // rows printed BLANK on this preliminary data sheet, so no OE_n // path is specified — 3-state transitions propagate with zero // delay rather than with invented values. endspecify endmodule