DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | MODE SELECT TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | AC OPERATING REQUIREMENTS
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Family: Fairchild FAST (Advanced Schottky TTL)
Source: 1985 Fairchild FAST Data Book, pages 4-88 ... 4-92
(shared data sheet with the 'F169, see 54F74F169.txt). The 1980
data book carries the 'F168 in its Section 3 selection guide
only (page 3-22, description and logic symbol).
Status: Released data sheet
Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C
The 'F168 and 'F169 are fully synchronous 4-stage up/down counters. The 'F168 is a BCD decade counter; the 'F169 is a modulo-16 binary counter. Both feature a preset capability for programmable operation, carry lookahead for easy cascading and a U//D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock. o Synchronous Counting and Loading o Built-In Lookahead Carry Capability o Presettable for Programmable Operation
The 'F168 and 'F169 use edge-triggered J-K type flip-flops and have no
constraints on changing the control or data input signals in either
state of the clock. The only requirement is that the various inputs
attain the desired state at least a setup time before the rising edge of
the clock and remain valid for the recommended hold time thereafter. The
parallel load operation takes precedence over other operations, as
indicated in the Mode Select Table. When /PE is LOW, the data on the
P0-P3 inputs enters the flip-flops on the next rising edge of the clock.
In order for counting to occur, both /CEP and /CET must be LOW and /PE
must be HIGH; the U//D input then determines the direction of counting.
The Terminal Count (/TC) output is normally HIGH and goes LOW, provided
that /CET is LOW, when a counter reaches zero in the Count Down mode or
reaches 9 (15 for the 'F169) in the Count Up mode. The /TC output state
is not a function of the Count Enable Parallel (/CEP) input level. The
/TC output of the 'F168 decade counter can also be LOW in the illegal
states 11, 13, and 15, which can occur when power is turned on or via
parallel loading. If an illegal state occurs, the 'F168 will return to
the legitimate sequence within two counts. Since the /TC signal is
derived by decoding the flip-flop states, there exists the possibility
of decoding spikes on /TC. For this reason the use of /TC as a clock
signal is not recommended (see logic equations below).
Logic equations
~~~~~~~~~~~~~~~
1) Count Enable = /CEP * /CET * /PE
2) Up: ('F168) /TC = Q0 * /Q1 * /Q2 * Q3 * (Up) * /CET
('F169) /TC = Q0 * Q1 * Q2 * Q3 * (Up) * /CET
3) Down: /TC = /Q0 * /Q1 * /Q2 * /Q3 * (Down) * /CET
State diagram
~~~~~~~~~~~~~
Normal sequence, Count Up: 0 -> 1 -> ... -> 9 -> 0.
Normal sequence, Count Down: 0 -> 9 -> ... -> 1 -> 0.
Illegal-state recovery:
Count Up: 10 -> 11 -> 6 Count Down: 10 -> 1
12 -> 13 -> 4 11 -> 10 -> 1
14 -> 15 -> 2 13 -> 12 -> 5
15 -> 14 -> 5
Pin Function Pin Function --- ----------------------------- --- --------------------------- 1 U//D Up/Down Count Control 16 Vcc 2 CP Clock Pulse 15 /TC Terminal Count output 3 P0 Parallel data input 0 14 Q0 Flip-flop output 0 4 P1 Parallel data input 1 13 Q1 Flip-flop output 1 5 P2 Parallel data input 2 12 Q2 Flip-flop output 2 6 P3 Parallel data input 3 11 Q3 Flip-flop output 3 7 /CEP Count Enable Parallel 10 /CET Count Enable Trickle 8 GND 9 /PE Parallel Enable CP is active on the rising edge of the clock.
/PE /CEP /CET U//D Action on Rising Clock Edge --- ---- ---- ---- --------------------------- L X X X Load (Pn -> Qn) H L L H Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold) H = HIGH voltage level; L = LOW voltage level; X = immaterial.
Pin Names Description U.L. HIGH/LOW ---------- ---------------------------------------- ------------- /CEP Count Enable Parallel Input (Active LOW) 0.5 / 0.375 /CET Count Enable Trickle Input (Active LOW) 0.5 / 0.75 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 P0 - P3 Parallel Data Inputs 0.5 / 0.375 /PE Parallel Enable Input (Active LOW) 0.5 / 0.375 U//D Up-Down Count Control Input 0.5 / 0.375 Q0 - Q3 Flip-Flop Outputs 25 / 12.5 /TC Terminal Count Output (Active LOW) 25 / 12.5
Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ---------- ICC Power Supply Current 35 52 mA Vcc = Max
TA = +25 C 74F
Vcc = +5.0V TA/Vcc = Com
Symbol Parameter CL Min Typ Max Min Max Units
------ ------------------------------- ----- --- --- --- --- ---- -----
fmax Maximum Clock Frequency -- 100 115 -- 90 -- MHz
tPLH Prop Delay CP to Qn 50 pF 3.0 6.5 8.5 3.0 9.5 ns
(/PE HIGH or LOW)
tPHL Prop Delay CP to Qn 50 pF 4.0 9.0 11.5 4.0 13.0 ns
(/PE HIGH or LOW)
tPLH Prop Delay CP to /TC 50 pF 5.5 12.0 15.5 5.5 17.0 ns
tPHL Prop Delay CP to /TC 50 pF 4.0 8.5 11.0 4.0 12.5 ns
tPLH Prop Delay /CET to /TC 50 pF 2.5 4.5 6.0 2.5 7.0 ns
tPHL Prop Delay /CET to /TC 50 pF 2.5 6.0 8.0 2.5 9.0 ns
tPLH Prop Delay U//D to /TC ('F168) 50 pF 3.5 8.5 11.0 3.5 12.5 ns
tPHL Prop Delay U//D to /TC ('F168) 50 pF 4.0 12.5 16.0 4.0 17.5 ns
TA = +25 C 74F
Vcc = +5.0V TA/Vcc = Com
Symbol Parameter Min Typ Max Min Max Units
------ --------------------------------------- --- --- --- --- --- -----
ts (H) Setup Time, HIGH -- Pn to CP 4.0 -- -- 4.5 -- ns
ts (L) Setup Time, LOW -- Pn to CP 4.0 -- -- 4.5 -- ns
th (H) Hold Time, HIGH -- Pn to CP 3.0 -- -- 3.5 -- ns
th (L) Hold Time, LOW -- Pn to CP 3.0 -- -- 3.5 -- ns
ts (H) Setup Time, HIGH -- /CEP or /CET to CP 5.0 -- -- 6.0 -- ns
ts (L) Setup Time, LOW -- /CEP or /CET to CP 5.0 -- -- 6.0 -- ns
th (H) Hold Time, HIGH -- /CEP or /CET to CP 0 -- -- 0 -- ns
th (L) Hold Time, LOW -- /CEP or /CET to CP 0 -- -- 0 -- ns
ts (H) Setup Time, HIGH -- /PE to CP 8.0 -- -- 9.0 -- ns
ts (L) Setup Time, LOW -- /PE to CP 8.0 -- -- 9.0 -- ns
th (H) Hold Time, HIGH -- /PE to CP 0 -- -- 0 -- ns
th (L) Hold Time, LOW -- /PE to CP 0 -- -- 0 -- ns
ts (H) Setup Time, HIGH -- U//D to CP ('F168) 11.0 -- -- 12.5 -- ns
ts (L) Setup Time, LOW -- U//D to CP ('F168) 16.5 -- -- 18.0 -- ns
th (H) Hold Time, HIGH -- U//D to CP 0 -- -- 0 -- ns
th (L) Hold Time, LOW -- U//D to CP 0 -- -- 0 -- ns
tw (H) CP Pulse Width, HIGH 5.0 -- -- 5.5 -- ns
tw (L) CP Pulse Width, LOW 5.0 -- -- 5.5 -- ns
Data sheet transcription as plain text
No model for this device yet — only the data sheet transcription above.